公开(公告)号：EP3167485A1

公开(公告)日：2017-05-17

申请号：EP14897417.3

申请日：2014-07-11

申请人： Intel Corporation

发明人： GANESAN, Sanka ,  ZIADEH, Bassam ,  NIMKAR, Nitesh

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L23/28

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了集成电路（IC）组件的可缩放封装体系结构以及相关技术和配置。 在一个实施例中，集成电路（IC）组件包括具有第一侧和与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和不活跃侧 与所述有源侧相对设置，所述第一裸片具有被配置为在所述第一裸片和第二裸片之间布线电信号的一个或多个硅通孔（TSV）以及布置在所述封装衬底的第一侧上的模制化合物，其中， 所述模制化合物在所述有效侧和所述无效侧之间与所述第一模具的侧壁直接接触，并且其中所述模制化合物的离所述第一侧最远的所述第一侧和终止边之间的距离等于或小于 比第一模具的不活动侧和第一侧之间的距离大。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP4020529A1

公开(公告)日：2022-06-29

申请号：EP21198864.7

申请日：2021-09-24

申请人： Intel Corporation

发明人： ZIADEH, Bassam ,  HUANG, Jingyi ,  BAI, Yiqun ,  LIN, Ziyin ,  MEHTA, Vipul ,  VAN NAUSDLE, Joseph

IPC分类号： H01L21/56

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.