公开(公告)号：EP3255668A1

公开(公告)日：2017-12-13

申请号：EP15888779.4

申请日：2015-04-14

申请人： Huawei Technologies Co., Ltd.

发明人： FU, Huili ,  ZHANG, Xiaodong ,  LIN, Jyh Rong ,  MA, Zhiqiang

IPC分类号： H01L23/522 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L21/563 ,  H01L21/568 ,  H01L23/367 ,  H01L23/48 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/5329 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/03 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/351

摘要： The present invention provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier; and the redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure. Therefore, there is no dissipation problem caused by superposition; in addition, it can be effectively ensured that a length of the signal path between the packaging function modules is not excessively long.

摘要翻译： 本发明提供一种芯片，包括载体，重分布结构和多个封装功能模块，所述多个封装功能模块每个至少有一部分被胶体包裹，并且并排固定在所述重分布结构上; 再分布结构固定到载体，并且再分布结构包括一个或多个再分布金属层; 再分布金属层通信连接多个封装功能模块和载体; 并且再分配结构进一步包括一个或多个互连金属层，并且互连金属层可通信地连接到至少两个封装功能模块，以提供在至少两个封装功能模块之间的信号路径。 在芯片中，两个封装功能模块并排放置在载体上，并且通过使用再分布结构在两个封装功能模块之间建立信号路径。 因此，不存在叠加造成的散热问题。 另外，可以有效保证封装功能模块之间的信号路径长度不会过长。

公开(公告)号：EP3167485A1

公开(公告)日：2017-05-17

申请号：EP14897417.3

申请日：2014-07-11

申请人： Intel Corporation

发明人： GANESAN, Sanka ,  ZIADEH, Bassam ,  NIMKAR, Nitesh

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L23/28

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了集成电路（IC）组件的可缩放封装体系结构以及相关技术和配置。 在一个实施例中，集成电路（IC）组件包括具有第一侧和与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和不活跃侧 与所述有源侧相对设置，所述第一裸片具有被配置为在所述第一裸片和第二裸片之间布线电信号的一个或多个硅通孔（TSV）以及布置在所述封装衬底的第一侧上的模制化合物，其中， 所述模制化合物在所述有效侧和所述无效侧之间与所述第一模具的侧壁直接接触，并且其中所述模制化合物的离所述第一侧最远的所述第一侧和终止边之间的距离等于或小于 比第一模具的不活动侧和第一侧之间的距离大。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP3152781A2

公开(公告)日：2017-04-12

申请号：EP15803526.1

申请日：2015-06-06

申请人： Rohinni, LLC ,  Huska, Andrew P. ,  Peterson, Cody G. ,  Christie, Kasey ,  Adams, Clinton ,  Ozias, Orin

发明人： HUSKA, Andrew ,  PETERSON, Cody ,  CHRISTIE, Kasey ,  ADAMS, Clint ,  OZIAS, Orin

IPC分类号： H01L21/50 ,  H01L25/03

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L25/03 ,  H01L2221/68327 ,  H01L2221/68354

摘要： An apparatus includes a carrier-to-circuit transfer mechanism that is configured to obtain one or more unpackaged semiconductor devices on a carrier substratum and directly transfer the one or more unpackaged semiconductor devices from the carrier substratum to a circuit assembly. The apparatus further includes an in-situ packager that is configured to in-situ package the one or more transferred devices by interconnecting each semiconductor device of the one or more transferred devices to conductive links of the circuit assembly and applying a coating material to the one or more transferred devices.

摘要翻译： 这里描述了与集成有半导体器件的电路的有效和有效的制造电子产品（例如，移动设备，计算机等）相关的技术。 如本文所述，新的制造方法在制造期间将未封装的半导体器件（即，裸片）合并到电子产品的电路中。 这是使用直接的载波到电路模转移方法完成的。 此外，将模具和/或其相关电路封装就地（即，“原位包装”）。 提交本摘要的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：EP3128549A1

公开(公告)日：2017-02-08

申请号：EP15773072.2

申请日：2015-03-12

申请人： Shin-Etsu Chemical Co., Ltd.

发明人： TAKEMURA, Katsuya ,  SOGA, Kyoko ,  ASAI, Satoshi ,  KONDO, Kazunori ,  SUGO, Michihiro ,  KATO, Hideto

IPC分类号： H01L23/12 ,  C25D5/02 ,  C25D7/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/11 ,  H05K3/28 ,  H05K3/40

CPC分类号： H01L23/12 ,  B23K1/0016 ,  B29C70/78 ,  B29C70/882 ,  B29K2063/00 ,  B29K2083/00 ,  B29K2105/20 ,  B29K2995/0005 ,  B29L2031/3493 ,  C23C14/042 ,  C23C14/34 ,  C23C14/58 ,  C25D3/60 ,  C25D5/022 ,  C25D5/48 ,  C25D5/505 ,  C25D5/54 ,  C25D7/00 ,  C25D7/123 ,  H01L21/02282 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2224/19 ,  H01L2224/83005

摘要： The present invention is a semiconductor apparatus including a semiconductor device, an on-semiconductor-device metal pad and a metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second insulating layer, wherein the metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second insulating layer, penetrates the second insulating layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second insulating layer, and an under-semiconductor-device metal interconnect is disposed between the first insulating layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower ' surface of the second insulating layer. This semiconductor apparatus can be easily placed on a circuit board and stacked, and can reduce its warpage even with dense metal interconnects.

摘要翻译： 本发明是一种半导体装置，导通半导体器件的金属焊盘和金属互连的每个电连接到所述半导体器件中，通过电极和焊料凸块的每个电连接到所述金属互连，第一绝缘的半导体装置 在其上的半导体器件被置于层，形成在半导体器件上形成第二绝缘层，形成在第二绝缘层上的第三绝缘层，worin金属互连电连接到所述半导体器件经由所述上半导体器件的金属垫 在在所述第二绝缘层的上表面上，贯穿其上表面上的第二绝缘层，以及电连接到所述贯通电极在在所述第二绝缘层的下表面上，并在下半导体器件的金属互连件之间设置 在第一绝缘层和所述半导体器件中，和下半导体的 设备金属互连在所述第二绝缘层的下部“表面电连接至所述金属互连。 该半导体装置可以被容易地放置在电路板上并堆叠，并能减少其翘曲即使致密的金属互连件。

公开(公告)号：EP3035012A3

公开(公告)日：2016-10-12

申请号：EP15197783.2

申请日：2015-12-03

申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

发明人： Erlbacher, Tobias

IPC分类号： H01L31/103 ,  H01L31/0312 ,  G01J1/42

CPC分类号： H01L31/1037 ,  B60H1/0075 ,  G01J1/02 ,  G01J1/42 ,  G01J1/429 ,  G01J2001/4266 ,  H01L25/03 ,  H01L27/1446 ,  H01L27/148 ,  H01L29/161 ,  H01L31/02161 ,  H01L31/02162 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L2924/0002 ,  H02S40/44 ,  H01L2924/00

摘要： Die vorliegende Erfindung betrifft ein Verfahren zur Detektion von Sonnenlicht (2) mit einer Detektoranordnung, die ein Ausgangssignal in Abhängigkeit von einfallendem Sonnenlicht liefert. Bei dem Verfahren wird eine Detektoranordnung mit einem SiC-Halbleiterdetektor (1) eingesetzt, der nur für den UV-Anteil des einfallenden Sonnenlichts (2) sensitiv ist. Durch den Einsatz einer derartigen Detektoranordnung wird eine Störung der Sonnenlichtdetektion durch künstliche Lichtquellen weitgehend vermieden, so dass eine zuverlässigere Detektion des Sonnenlichts (2) ermöglicht wird.

公开(公告)号：EP2937900A2

公开(公告)日：2015-10-28

申请号：EP15001129.4

申请日：2015-04-17

申请人： Broadcom Corporation

发明人： Law, Edward ,  Khan, Rezaur ,  Hu, Kunzhong

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10 ,  H01L25/03 ,  H01L25/065 ,  H01L23/552 ,  H01L23/29 ,  H01L21/98

CPC分类号： H01L25/0655 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Reconstitution techniques for semiconductor packages are provided. One reconstitution technique is used to encapsulate (348) a plurality of semiconductor packages (336,354,356) into a single multi-chip module (fig. 3e). Solder balls (326) coupled to each package may be partially exposed after reconstitution, which enables the packages to be coupled to another device. Another reconstitution technique is used to couple a plurality of semiconductor packages into a package-on-package module using self-alignment feature(s) (fig. 6k). The self-alignment feature(s) are exposed solder ball(s) (626) that are included in the bottom package of the package-on-package module. The exposed solder ball(s) serve as a frame of reference to other solder balls (624) that are encapsulated by an encapsulation material (634). After the location of these other solders balls are determined, through-mold vias (636a,636b) may be formed in the encapsulation material at locations corresponding to the other solder balls. The top package of the package-on-package module may then be coupled to the bottom package using these solder balls.

摘要翻译： 提供了半导体封装的重构技术。 一种重构技术用于将多个半导体封装（336,354,356）封装（348）成单个多芯片模块（图3e）。 耦合到每个封装的焊球（326）可以在重构之后部分暴露，这使封装能够耦合到另一个器件。 使用另一种重构技术来使用自对准特征（多个）将多个半导体封装耦合到封装级封装模块（图6k）。 自对准特征是包装在层叠封装模块的底部封装中的暴露的焊球（626）。 暴露的焊球用作由封装材料（634）封装的其他焊球（624）的参照系。 在确定了这些其他焊料球的位置之后，可以在对应于其他焊料球的位置处在封装材料中形成贯通模通孔（636a，636b）。 然后，使用这些焊球将堆叠封装模块的顶部封装耦合到底部封装。

公开(公告)号：EP2752873A3

公开(公告)日：2014-09-24

申请号：EP14162557.4

申请日：2013-02-28

申请人： J-Devices Corporation

发明人： Umeki, Akihiro ,  Hiruta, Yoichi

IPC分类号： H01L25/03 ,  H01L25/065 ,  H01L21/66

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module, having a semiconductor package, which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip; and a second package substrate; wherein the semiconductor package is mounted on the second package substrate and the semiconductor bare chip is mounted on the semiconductor package, wherein the semiconductor package is bonded to the second package substrate at the resin surface and electrically connected to the second package substrate by wire bonding.

公开(公告)号：EP2645417A1

公开(公告)日：2013-10-02

申请号：EP13157205.9

申请日：2013-02-28

申请人： J-Devices Corporation

发明人： Umeki, Akihiro ,  Hiruta, Yoichi

IPC分类号： H01L25/03 ,  H01L25/065

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved.
A semiconductor module (10), having: a semiconductor package (6), which is obtained by mounting and resin-sealing a semiconductor bare chip (1) on a first package substrate (4); a semiconductor bare chip 2; and a second package substrate (12), the semiconductor module being characterized in that the semiconductor package (6) is mounted on the second package substrate (12) and the semiconductor bare chip (2) is mounted on the semiconductor package (6).

摘要翻译： 在包括封装基板，第一半导体封装和半导体裸芯片的半导体模块中，在树脂密封时出现由第一半导体封装的翘曲引起的引线短路等的问题 可以解决 一种半导体模块（10），具有：半导体封装（6），其通过将半导体裸芯片（1）安装并树脂密封在第一封装基板（4）上而获得; 半导体裸芯片2; 和第二封装基板（12），所述半导体模块的特征在于，所述半导体封装（6）安装在所述第二封装基板（12）上，所述半导体裸芯片（2）安装在所述半导体封装（6）上。

公开(公告)号：EP1732127A3

公开(公告)日：2011-05-18

申请号：EP06114626.2

申请日：2006-05-29

申请人： IMEC

发明人： BEYNE, Eric

IPC分类号： H01L21/98 ,  H01L21/60 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention is related to A method for bonding elements (1,1') comprising the steps of
- producing on a main surface of a first element a first solder ball (3),
- producing on a main surface of a second element a second solder ball (3'),
- providing contact between said first solder ball (3) and said second solder ball (3'),
- bonding said first element (1) and said second element (1') by applying a reflow step whereby said solder balls melt and form a joined solder ball structure (7)
wherein
- prior to the bonding step, the first solder ball (3)is laterally embedded in a layer (4) of non-conductive material, such that the upper part of said first solder ball is not covered by said non-conductive material, and
- said layer (4) of non-conductive material is laterally embedding said first solder ball (3) up to a level parallel to the main surface of the first element.

公开(公告)号：EP1990833A2

公开(公告)日：2008-11-12

申请号：EP08161671.6

申请日：2001-01-12

申请人： IBIDEN CO., LTD.

发明人： Sakamoto, H. c/o Ogaki-kita-kojou Ibiden Co., Ltd. ,  Sugiyama, T. c/o Ogaki-kita-kojou Ibiden Co., Ltd. ,  Wang, D. c/o Ogaki-kita-kojou Ibiden Co., Ltd. ,  Kariya, T. c/o Ogaki-kita-kojou Ibiden Co., Ltd.

IPC分类号： H01L23/538 ,  H01L23/498

CPC分类号： H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

摘要： A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

摘要翻译： 多层印刷电路板具有预先包括在核心基板30中的IC芯片20和设置在IC芯片20的焊盘24上的过渡层38.由此，可以将IC芯片电连接到多层 印刷电路板而不使用引线部件和密封树脂。 另外，通过在芯片焊盘24上设置由铜构成的过渡层38，能够防止焊盘24上的树脂残渣，能够提高焊盘24与过孔60的连接性和可靠性。