专利检索 cpc:"H01L2224/9211" 第 1 页

1.

发明公开
ASSEMBLING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF FLIP-DIE 审中-公开

公开(公告)号：EP3221882A4

公开(公告)日：2018-05-02

申请号：EP15897979

申请日：2015-07-14

申请人： GOERTEK INC

发明人： ZOU QUANBO , WANG ZHE

IPC分类号： H01L21/60 , H01L21/66 , H01L21/683

CPC分类号： H01L24/97 , H01L21/50 , H01L21/6835 , H01L22/14 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0753 , H01L33/62 , H01L2221/68318 , H01L2221/68327 , H01L2221/68354 , H01L2221/68381 , H01L2224/131 , H01L2224/16227 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/2939 , H01L2224/32013 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81121 , H01L2224/81143 , H01L2224/81191 , H01L2224/81815 , H01L2224/81903 , H01L2224/81907 , H01L2224/83005 , H01L2224/83101 , H01L2224/83143 , H01L2224/83851 , H01L2224/83855 , H01L2224/92 , H01L2224/9211 , H01L2224/92125 , H01L2224/94 , H01L2224/95001 , H01L2224/95144 , H01L2224/95145 , H01L2224/97 , H01L2924/12041 , H01L2933/0033 , H01L2933/0066 , H01L2224/11 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2221/68304 , H01L21/78 , H01L22/10 , H01L2224/83104 , H01L2924/014

摘要： The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a flip-die, comprises: temporarily bonding the flip-die onto a laser-transparent first substrate, wherein bumps of the flip-die are located on the side of the flip-die opposite to the first substrate; aligning the bumps with pads on a receiving substrate; irradiating the original substrate with laser from the first substrate side to lift-off the flip-die from the first substrate; and attaching the flip-die on the receiving substrate. A faster assembly rate can be achieved by using the present invention. A smaller chip size can be achieved by using the present invention. A lower profile can be achieved by using the present invention.

2.

发明公开
IMPROVEMENTS IN OR RELATING TO CONTACT SMART CARDS 审中-公开
标题翻译：关于联系人智能卡的改进或与之相关的改进

公开(公告)号：EP3270328A1

公开(公告)日：2018-01-17

申请号：EP17182828.8

申请日：2014-04-09

申请人： Johnson Electric S.A.

发明人： Demaso, Arthur , De Loi, Teck , Salle, Vincent

IPC分类号： G06K19/077

CPC分类号： G06K19/07743 , G06K19/022 , G06K19/07722 , H01L23/49855 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/97 , H01L2224/0401 , H01L2224/1134 , H01L2224/1146 , H01L2224/13019 , H01L2224/16227 , H01L2224/2731 , H01L2224/2732 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81395 , H01L2224/81455 , H01L2224/8149 , H01L2224/81903 , H01L2224/83101 , H01L2224/83192 , H01L2224/8385 , H01L2224/83851 , H01L2224/9211 , H01L2224/95115 , H01L2924/15313 , H05K3/244 , H01L2924/00014 , H01L2924/0781 , H01L2224/81 , H01L2224/83

摘要： A contact smart card (100, 101) comprises a smart card contact pad (10) and an IC chip (200, 300). The smart card contact pad 10 includes an imageable circuit substrate (12), a card-reader contact element (14) on a first side (16) of the imageable circuit substrate (12), and a, preferably flip-chip, connection element (18) on a second side (20) of the imageable circuit substrate (12) which is opposite the first side (16). The card-reader contact element (14) has a noble metal electrically conductive surface (30), and the connection element (18) has a chip terminal connection surface (36) which is not a noble metal. The IC chip (200, 300) is preferably flip-chip mounted at the second side (20) of the imageable circuit substrate (12) and electrically connected to the chip terminal connection surface (36). Furthermore, the chip terminal connection surface is preferably an organometallic electrically conductive corrosion protection layer.

摘要翻译： 接触式智能卡（100,101）包括智能卡接触垫（10）和IC芯片（200,300）。智能卡接触垫10包括可成像电路基板（12），可成像电路基板（12）的第一侧（16）上的卡读取器接触元件（14），以及优选为倒装芯片的连接元件（18）在所述可成像电路基板（12）的与所述第一侧（16）相对的第二侧（20）上。读卡器接触元件（14）具有贵金属导电表面（30），并且连接元件（18）具有不是贵金属的芯片端子连接表面（36）。 IC芯片（200,300）优选倒装安装在可成像电路基板（12）的第二侧（20）处并电连接到芯片端子连接表面（36）。此外，芯片端子连接表面优选为有机金属导电腐蚀保护层。

3.

发明公开
ASSEMBLING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF FLIP-DIE 审中-公开
标题翻译：组装方法，制造方法，装置和翻转模的电子装置

公开(公告)号：EP3221882A1

公开(公告)日：2017-09-27

申请号：EP15897979.9

申请日：2015-07-14

申请人： Goertek Inc.

发明人： ZOU, Quanbo , WANG, Zhe

IPC分类号： H01L21/50

CPC分类号： H01L24/97 , H01L21/50 , H01L21/6835 , H01L22/14 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0753 , H01L33/62 , H01L2221/68318 , H01L2221/68327 , H01L2221/68354 , H01L2221/68381 , H01L2224/131 , H01L2224/16227 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/2939 , H01L2224/32013 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81011 , H01L2224/81121 , H01L2224/81143 , H01L2224/81191 , H01L2224/81815 , H01L2224/81903 , H01L2224/81907 , H01L2224/83005 , H01L2224/83101 , H01L2224/83143 , H01L2224/83851 , H01L2224/83855 , H01L2224/92 , H01L2224/9211 , H01L2224/92125 , H01L2224/94 , H01L2224/95001 , H01L2224/95144 , H01L2224/95145 , H01L2224/97 , H01L2924/12041 , H01L2933/0033 , H01L2933/0066 , H01L2224/11 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2221/68304 , H01L21/78 , H01L22/10 , H01L2224/83104 , H01L2924/014

摘要： The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a flip-die, comprises: temporarily bonding the flip-die onto a laser-transparent first substrate, wherein bumps of the flip-die are located on the side of the flip-die opposite to the first substrate; aligning the bumps with pads on a receiving substrate; irradiating the original substrate with laser from the first substrate side to lift-off the flip-die from the first substrate; and attaching the flip-die on the receiving substrate. A faster assembly rate can be achieved by using the present invention. A smaller chip size can be achieved by using the present invention. A lower profile can be achieved by using the present invention.

摘要翻译： 公开了一种倒装芯片的组装方法，制造方法，装置和电子装置。用于组装翻转模的方法包括：将翻转模（205）暂时接合到激光透明的第一基板（204）上，其中翻转模（205）的凸块（202）位于激光透过的第一基板与所述第一基板（204）相对的所述翻转模（205）; 将凸块（202）与衬垫（206）对准在接收衬底（207）上; 用激光（208）从所述第一衬底侧照射所述原始衬底以从所述第一衬底（204）剥离所述倒装管芯（205）; 并将翻转模（205）附着在接收基板（207）上。可以实现更快的组装速度，更小的芯片尺寸和更低的外形。

4.

发明授权
METHODS AND SYSTEMS FOR MATERIAL BONDING 有权
标题翻译：用于材料结合的方法和系统

公开(公告)号：EP2340554B1

公开(公告)日：2017-05-10

申请号：EP09783180.4

申请日：2009-09-18

申请人： IMEC

发明人： ZHANG, Wenqi , BEYNE, Eric

IPC分类号： H01L21/60 , H01L23/485 , H01L25/065

CPC分类号： H01L25/50 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/291 , H01L2224/29111 , H01L2224/32507 , H01L2224/81203 , H01L2224/81208 , H01L2224/81801 , H01L2224/81894 , H01L2224/83099 , H01L2224/83801 , H01L2224/83894 , H01L2224/9211 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/3512 , H01L2924/00 , H01L2924/00014

5.

发明公开
MULTI-CHIP MODULE WITH A COMPRESSIBLE STRUCTURE FOR MAINTAINING ALIGNMENT BETWEEN CHIPS IN THE MODULE 有权
标题翻译：可压缩结构更为芯片模块用于维持对准芯片之间在模块

公开(公告)号：EP2959509A4

公开(公告)日：2016-11-02

申请号：EP13707504

申请日：2013-02-14

申请人： NANOPAREIL LLC , MENKHAUS TODD , FONG HAO

发明人： MENKHAUS TODD , FONG HAO

IPC分类号： D01F2/24 , B01D15/38 , D01F6/44 , D01F6/88

CPC分类号： B01D39/1615 , B01D15/327 , B01D15/361 , B01D15/3804 , B01D15/3809 , B01D39/1623 , B01D39/1676 , B01D2239/025 , B01D2239/0414 , B01J20/24 , B01J20/28007 , B01J20/28038 , B01J20/3212 , B01J20/3217 , B01J20/3248 , B01J20/3293 , C07K1/22 , D01D5/0007 , D01D5/003 , D01F2/24 , D01F6/44 , D01F6/88 , H01L23/48 , H01L24/16 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/91 , H01L25/0652 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/73201 , H01L2224/81138 , H01L2224/81815 , H01L2224/9211 , H01L2225/06517 , H01L2225/06527 , H01L2225/06531 , H01L2225/06562 , H01L2225/06593 , H01L2924/0002 , H01L2924/15153 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/3511 , H01L2924/37001 , H01L2924/00 , H01L2924/014 , H01L2224/16 , H01L2224/72 , H01L2224/81 , H01L2224/90 , H01L2924/00014 , H01L2924/00012

摘要： The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

6.

发明公开
NOVEL BONDING PROCESS AND BONDED STRUCTURES 审中-公开
标题翻译：胶新方法及粘接构造

公开(公告)号：EP2425450A4

公开(公告)日：2016-10-05

申请号：EP10770036

申请日：2010-04-30

申请人： SILEX MICROSYSTEMS AB

发明人： EBEFORS THORBJÖRN , KÄLVESTEN EDWARD , SVEDIN NIKLAS , ERIKSSON ANDERS

IPC分类号： H01L23/10 , B81B7/00 , B81C1/00

CPC分类号： H01L23/10 , B81C1/00269 , B81C2203/0118 , B81C2203/019 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/13144 , H01L2224/29035 , H01L2224/29111 , H01L2224/29144 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/83805 , H01L2224/9211 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/1461 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2224/0401

摘要： A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.