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公开(公告)号：EP0470500A1
公开(公告)日：1992-02-12
申请号：EP91112899.9
申请日：1991-07-31
发明人： Kimura, Masahiro, c/o Intellectual Property Div. , Matsuo, Kenji, c/o Intellectual Property Div. , Tsuchiya, Ikuo, c/o Intellectual Property Div. , Fukuda, Masayo, c/o Intellectual Property Div.
IPC分类号： H03K19/003
CPC分类号： H03K19/00353
摘要： A low-noise output buffer circuit of this invention comprises a P-channel MOSFET (102) having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET (103) having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor (105) having a collector connected to the power source potential, an emitter connected to an output terminal (106) and a base connected to the drain of the P-channel MOSFET, and a diode (107) having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.
摘要翻译： 本发明的低噪声输出缓冲电路包括：具有连接到电源电位的源极的P沟道MOSFET（102），用于根据第一输入信号输出电源电位; N沟道MOSFET（103） 具有连接到地电位的源，用于根据第二输入信号输出接地电位;双极晶体管（105），其具有连接到电源电位的集电极;发射极连接到输出端子（106）和基极 连接到P沟道MOSFET的漏极，并且具有连接到N沟道MOSFET的漏极的阴极和连接到NPN双极晶体管的基极的阳极的二极管（107）。
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公开(公告)号：EP0470500B1
公开(公告)日：1998-10-07
申请号：EP91112899.9
申请日：1991-07-31
发明人： Kimura, Masahiro, c/o Intellectual Property Div. , Matsuo, Kenji, c/o Intellectual Property Div. , Tsuchiya, Ikuo, c/o Intellectual Property Div. , Fukuda, Masayo, c/o Intellectual Property Div.
IPC分类号： H03K19/003
CPC分类号： H03K19/00353
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公开(公告)号：EP0387792A1
公开(公告)日：1990-09-19
申请号：EP90104728.2
申请日：1990-03-13
发明人： Matsuo, Kenji, c/o Intellectual Property Div. , Tsuchiya, Ikuo, c/o Intellectual Property Div. , Kimura, Masahiro, c/o Intellectual Property Div. , Ookawauchi, Tadahisa, c/o Int. Property Div.
IPC分类号： H03K19/0175 , H03K19/08
CPC分类号： H03K19/017581 , H03K19/00353 , H03K19/017518
摘要： An output buffer circuit includes an input node (1), an output node (2), a positive power source (V DD ), a logic circuit (10) connected to the input node (1), means (11) connected at one end to the logic circuit (10), for dropping a voltage of the logic circuit (10), and a bipolar transistor (12) having a base connected to the other end of the voltage dropping means (11) and the other end of the logic circuit (10), a collector connected to the output node (2) and an emitter connected to a circuit ground (GND).
摘要翻译： 一种输出缓冲器电路，包括输入节点（1），输出节点（2），正电源（VDD），连接到输入节点（1）的逻辑电路（10） （10）的电压降低的逻辑电路（10），以及具有与降压装置（11）的另一端连接的基极和逻辑电路（10）的另一端的双极型晶体管 电路（10），连接到输出节点（2）的集电极和连接到电路接地（GND）的发射极。
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4.发明公开Shape of bonding pad of semiconductor device bonded by wire bonding method 失效形式eines Kontaktfleckes einer Halbleiteranordnung zum Binden mittels eines Drahtbondverfahrens。
公开(公告)号：EP0488186A1
公开(公告)日：1992-06-03
申请号：EP91120207.5
申请日：1991-11-26
发明人： Kunieda, Mitsuyuki, c/o Intellectual Property Div. , Tsuchiya, Ikuo, c/o Intellectual Property Div. , Maruyama, Junko, c/o Intellectual Property Div.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06179 , H01L2224/48247 , H01L2224/4847 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/49179 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip (100) is die-bonded to a bed (101) of a lead frame. Bonding pads (102) are formed on the semiconductor chip (100) along its periphery. The bonding pads (102) have at least one obtuse-angle corner portion of corner portions facing a nearest side of the chip (100). Each of the bonding pads (102) is bonded to an inner lead portion (106) of the lead frame by a bonding wire (104).
摘要翻译： 半导体芯片（100）被芯片接合到引线框架的床（101）上。 接合焊盘（102）沿其周边形成在半导体芯片（100）上。 接合焊盘（102）具有面向芯片（100）的最近侧的角部的至少一个钝角角部。 每个接合焊盘（102）通过接合线（104）接合到引线框架的内引线部分（106）。
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