公开(公告)号：EP1460681A3

公开(公告)日：2007-11-28

申请号：EP04006581.5

申请日：2004-03-18

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

公开(公告)号：EP1460681A2

公开(公告)日：2004-09-22

申请号：EP04006581.5

申请日：2004-03-18

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

摘要翻译： 本发明的半导体器件具有：碳化硅衬底1; n型高电阻层2; 设置在高电阻层2的表面区域中的阱区域3; 设置在每个阱区域3内的p +接触区域4; 源区域5，其设置成横向围绕每个阱区域3内的p +接触区域4; 设置在源极区域5上并由镍制成的第一源电极8; 覆盖第一源电极8并由铝制成的第二源电极9; 设置在夹在两个阱区域3之间的高电阻层2的一部分上的栅极绝缘膜6; 由铝制成的栅电极10; 以及覆盖第二源电极9和栅电极10并由氧化硅制成的层间电介质膜11。

公开(公告)号：EP1265295A2

公开(公告)日：2002-12-11

申请号：EP02012326.1

申请日：2002-06-04

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Uchida, Masao ,  Kitabatake, Makoto ,  Yokogawa, Toshiya ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Miyanaga, Ryoko ,  Yamashita, Kenya

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor substrate made of 4H-SiC, an epitaxially grown 4H-SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

公开(公告)号：EP1032048A1

公开(公告)日：2000-08-30

申请号：EP00103360.4

申请日：2000-02-22

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Takahashi, Kunimasa ,  Uenoyama, Takeshi

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/049 ,  H01L29/66068

摘要： An insulated-gate semiconductor element having a high breakdown voltage is provided. The surface of a silicon carbide substrate is etched to form a concave portion. A particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. A gate electrode is formed on the oxide film. The oxide film at the bottom surface is thicker than at the side surfaces, so that a high breakdown voltage can be ensured, even when the surface of the silicon carbide layer is a face with which a superior epitaxial layer can be attained, such as the (111) Si-face of β -SiC or the (0001) Si-face of α -SiC.

摘要翻译： 提供具有高击穿电压的绝缘栅半导体元件。 蚀刻碳化硅衬底的表面以形成凹部。 从上方照射粒子束，例如离子束，至少在凹部的底面形成有缺陷层。 在氧化气氛中加热基板，至少在凹部的侧面和底面形成氧化膜。 在氧化膜上形成栅电极。 底面的氧化膜比侧面厚，因此即使当碳化硅层的表面是能够获得优异的外延层的面时，也能够确保高的击穿电压，例如 （111）β-SiC的Si面或α-SiC的（0001）Si面。

公开(公告)号：EP1209740A3

公开(公告)日：2008-03-19

申请号：EP01127726.6

申请日：2001-11-21

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Yokogawa, Toshiya ,  Takahashi, Kunimasa ,  Uchida, Masao ,  Kitabatake, Makoto ,  Kusumoto, Osamu

IPC分类号： H01L21/82 ,  H01L27/06

CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of δ-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of δ - doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the δ -doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

公开(公告)号：EP1143526A3

公开(公告)日：2005-09-28

申请号：EP01303280.0

申请日：2001-04-06

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Yokogawa, Toshiya ,  Takahashi, Kunimasa ,  Kusumoto, Osamu

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/20 ,  H01L21/04 ,  H01L21/336

CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate 11, an n-type semiconductor layer 12 formed on the n-type substrate 11, a p-type semiconductor layer 13 formed on the n-type semiconductor layer 12, a p-type region 14 embedded in the n-type semiconductor layer 12, an n-type region 15 embedded in the n-type semiconductor layer 12 and the p-type semiconductor layer 13, an n-type source region 16 disposed in the p-type semiconductor layer 13 on its surface side, an insulating layer 17 disposed on the p-type semiconductor layer 13, a gate electrode 18 disposed on the insulating layer 17, a source electrode 19, and a drain electrode 20. The n-type semiconductor layer 12, the p-type semiconductor layer 13, and the p-type region 14 are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.

摘要翻译： 提供了具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底11，形成在n型衬底11上的n型半导体层12，形成在n型半导体层12上的p型半导体层13，p型区域 嵌入在n型半导体层12中的n型区域15，嵌入在n型半导体层12和p型半导体层13中的n型区域15，设置在p型半导体层 在绝缘层17上设置绝缘层17，设置在绝缘层17上的栅电极18，源电极19和漏电极20. n型半导体层12， p型半导体层13和p型区域14分别由具有至少2eV的带隙的宽间隙半导体制成。

公开(公告)号：EP0706196B1

公开(公告)日：2000-03-01

申请号：EP95115520.9

申请日：1995-10-02

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tanaka, Hiroyoshi ,  Kotera, Koichi ,  Uchida, Masao

IPC分类号： H01J1/30 ,  H01J9/02 ,  H01J45/00

CPC分类号： B82Y10/00 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2329/00

公开(公告)号：EP0706196A2

公开(公告)日：1996-04-10

申请号：EP95115520.9

申请日：1995-10-02

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tanaka, Hiroyoshi ,  Kotera, Koichi ,  Uchida, Masao

IPC分类号： H01J1/30 ,  H01J9/02

CPC分类号： B82Y10/00 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2329/00

摘要： An electron emission cathode includes: an n-type semiconductor film including diamond particles partially projecting from a surface of the n-type semiconductor film; and an anode opposing the n-type semiconductor film with a vacuum interposed therebetween. Electrons are emitted by applying a voltage between the anode and the n-type semiconductor film. Furthermore, an electron emission cathode includes: a conductive film
   a first semiconductor film of a first conductivity type formed on the conductive film;
   an island-like second semiconductor film of a second conductivity type formed on the first semiconductor film; and
   an anode opposing the conductive film with a vacuum interposed therebetween,
   wherein electrons are emitted by applying a voltage between the anode and the second semiconductor film.
Furthermore, a thermoelectric cooling device is disclosed.

摘要翻译： 一种电子发射阴极包括：一个n型半导体膜 - 包括金刚石颗粒从n型半导体成膜的表面上部分地突出; 并与阳极相对的n型半导体膜与之间插入有一真空。 电子由阳极与n型半导体电影之间施加电压使电子发射。 进一步，向电子发射阴极包括：一个导电膜形成在该导电膜上的第一导电类型的第一半导体电影; 到在第一半导体FORMED电影的第二导电类型的冰岛状的第二半导体电影; 并与阳极相对的所述导电膜与之间插入有一真空，worin电子由阳极及第二半导体电影之间施加电压使电子发射。 进一步，热电冷却装置是游离缺失光盘。

公开(公告)号：EP1968104A2

公开(公告)日：2008-09-10

申请号：EP08011174.3

申请日：2003-07-09

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya c/o Matsushita Electric Industrial Co., Ltd ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L21/336 ,  H01L21/82 ,  H01L29/872 ,  H01L29/812 ,  H01L29/45 ,  H01L27/06 ,  H01L29/772

CPC分类号： H01L29/7813 ,  H01L21/0485 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931

摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

摘要翻译： 累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有形成在阱区103的表面区域上的多重掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 并且栅极电极110.累积沟道层104具有这样的结构，其中，在量子效应下允许载流子向未掺杂层104b扩展移动的未掺杂层104b和“掺杂层104a被交替堆叠。 提供源电极111，其进入累积沟道层104和接触区域105以与接触区域105直接接触。通过离子注入不需要形成源极区域，导致制造成本降低。

公开(公告)号：EP1494268A2

公开(公告)日：2005-01-05

申请号：EP04015637.4

申请日：2004-07-02

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Uchida, Masao ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Hagio, Masahiro ,  Sawada, Kazuyuki

IPC分类号： H01L21/04

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的一部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。