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    Field effect transistor and method of manufacturing the same
    2.
    发明公开
    Field effect transistor and method of manufacturing the same 审中-公开
    Feldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1143526A3

    公开(公告)日：2005-09-28

    申请号：EP01303280.0

    申请日：2001-04-06

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Yokogawa, Toshiya ,  Takahashi, Kunimasa ,  Kusumoto, Osamu

    IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/20 ,  H01L21/04 ,  H01L21/336

    CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

    摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate 11, an n-type semiconductor layer 12 formed on the n-type substrate 11, a p-type semiconductor layer 13 formed on the n-type semiconductor layer 12, a p-type region 14 embedded in the n-type semiconductor layer 12, an n-type region 15 embedded in the n-type semiconductor layer 12 and the p-type semiconductor layer 13, an n-type source region 16 disposed in the p-type semiconductor layer 13 on its surface side, an insulating layer 17 disposed on the p-type semiconductor layer 13, a gate electrode 18 disposed on the insulating layer 17, a source electrode 19, and a drain electrode 20. The n-type semiconductor layer 12, the p-type semiconductor layer 13, and the p-type region 14 are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.

    摘要翻译： 提供了具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底11，形成在n型衬底11上的n型半导体层12，形成在n型半导体层12上的p型半导体层13，p型区域 嵌入在n型半导体层12中的n型区域15，嵌入在n型半导体层12和p型半导体层13中的n型区域15，设置在p型半导体层 在绝缘层17上设置绝缘层17，设置在绝缘层17上的栅电极18，源电极19和漏电极20. n型半导体层12， p型半导体层13和p型区域14分别由具有至少2eV的带隙的宽间隙半导体制成。

    Silicon carbide semiconductor device and method for fabricating the same
    4.
    发明公开
    Silicon carbide semiconductor device and method for fabricating the same 有权
    Siliziumkarbidhalbleiterbauelement和Verfahren zu dessen Herstellung

    公开(公告)号：EP1460681A2

    公开(公告)日：2004-09-22

    申请号：EP04006581.5

    申请日：2004-03-18

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

    IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

    CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

    摘要翻译： 本发明的半导体器件具有：碳化硅衬底1; n型高电阻层2; 设置在高电阻层2的表面区域中的阱区域3; 设置在每个阱区域3内的p +接触区域4; 源区域5，其设置成横向围绕每个阱区域3内的p +接触区域4; 设置在源极区域5上并由镍制成的第一源电极8; 覆盖第一源电极8并由铝制成的第二源电极9; 设置在夹在两个阱区域3之间的高电阻层2的一部分上的栅极绝缘膜6; 由铝制成的栅电极10; 以及覆盖第二源电极9和栅电极10并由氧化硅制成的层间电介质膜11。

    Insulated-gate semiconductor element and method for manufacturing the same
    6.
    发明公开
    Insulated-gate semiconductor element and method for manufacturing the same 有权
    HerstellungsverfahrenfürHalbleiterbauelement mit isoliertem Gate

    公开(公告)号：EP1032048A1

    公开(公告)日：2000-08-30

    申请号：EP00103360.4

    申请日：2000-02-22

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Takahashi, Kunimasa ,  Uenoyama, Takeshi

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L29/423 ,  H01L21/265

    CPC分类号： H01L29/7813 ,  H01L21/049 ,  H01L29/66068

    摘要： An insulated-gate semiconductor element having a high breakdown voltage is provided. The surface of a silicon carbide substrate is etched to form a concave portion. A particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. A gate electrode is formed on the oxide film. The oxide film at the bottom surface is thicker than at the side surfaces, so that a high breakdown voltage can be ensured, even when the surface of the silicon carbide layer is a face with which a superior epitaxial layer can be attained, such as the (111) Si-face of β -SiC or the (0001) Si-face of α -SiC.

    摘要翻译： 提供具有高击穿电压的绝缘栅半导体元件。 蚀刻碳化硅衬底的表面以形成凹部。 从上方照射粒子束，例如离子束，至少在凹部的底面形成有缺陷层。 在氧化气氛中加热基板，至少在凹部的侧面和底面形成氧化膜。 在氧化膜上形成栅电极。 底面的氧化膜比侧面厚，因此即使当碳化硅层的表面是能够获得优异的外延层的面时，也能够确保高的击穿电压，例如 （111）β-SiC的Si面或α-SiC的（0001）Si面。

    SEMICONDUCTOR ELEMENT
    7.
    发明公开
    SEMICONDUCTOR ELEMENT 审中-公开
    HALBLEITERELEMENT

    公开(公告)号：EP1689000A1

    公开(公告)日：2006-08-09

    申请号：EP04819378.3

    申请日：2004-11-24

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Uchida, Masao ,  Kitabatake, Makoto ,  Kusumoto, Osamu ,  Yamashita, Kenya ,  Takahashi, Kunimasa ,  Miyanaga, Ryoko

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

    摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction.
    In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

    摘要翻译： 在本发明的半导体器件中，形成在碳化硅衬底上的n型碳化硅层的顶表面从（0001）面向<11-20>方向错开。 栅电极，源电极等元件被布置成使得在通道区域中，主导电流沿着误差方向流动。 在本发明中，形成栅极绝缘膜，然后在含有V族元素的气氛中进行热处理。 以这种方式，碳化硅层和栅极绝缘膜之间的界面处的界面态密度降低。 结果，电子迁移率在错误方向A上比在与错误方向A垂直的方向上更高。

    Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
    8.
    发明公开
    Silicon carbide-oxide layered structure, production method thereof, and semiconductor device 有权
    Herstellungsverfahren einer Siliziumkarbidoxid-Schichtstruktur

    公开(公告)号：EP1523032A2

    公开(公告)日：2005-04-13

    申请号：EP04023713.3

    申请日：2004-10-05

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Yamashita, Kenya ,  Kitabatake, Makoto ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Uchida, Masao ,  Miyanaga, Ryoko

    IPC分类号： H01L21/04

    CPC分类号： H01L29/518 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/7828

    摘要： A gate insulating film which is an oxide layer mainly made of SiO 2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100°C and lower than 1250°C, whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

    摘要翻译： 通过热氧化在碳化硅衬底上形成作为主要由SiO 2形成的氧化物层的栅极绝缘膜，然后将所得到的结构在室内的惰性气体气氛中进行退火。 此后，将碳化硅 - 氧化物层状结构放置在具有真空泵的室中，在高于1100℃且低于1250℃的高温下暴露于减压NO气体气氛中，从而在 栅极绝缘膜。 结果，得到作为含有氧化物层的V族元素的栅极绝缘膜，其下部具有高的氮浓度区域，其相对介电常数为3.0以上。 含V族元素的氧化物层和碳化硅层之间的界面区域的界面态密度降低。

    SiC-misfet and method for fabricating the same
    9.
    发明公开
    SiC-misfet and method for fabricating the same 审中-公开
    SiC-misfet和Verfahren zur dessen Herstellung

    公开(公告)号：EP1429392A2

    公开(公告)日：2004-06-16

    申请号：EP03027344.5

    申请日：2003-11-26

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takahashi, Kunimasa ,  Kusumoto, Osamu ,  Kitabatake, Makoto ,  Uchida, Masao ,  Yamashita, Kenya

    IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L21/04

    CPC分类号： H01L29/7828 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838

    摘要： A storage-type (accumulation-type) SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is a storage-type (accumulation-type) channel layer, a p-type heavily doped contact layer to contact the well layer, a gate insulation film, a gate electrode. The storage-type SiC-MISFET is characterized by a heavily doped layer formed by implanting ions of a p-conductivity type into an upper surface portion of the n-type drift layer at a higher concentration than that in the well region, before the formation of the channel layer. The planar gate SiC-MISFET can be of the vertical or of the horizontal type.

    摘要翻译： 存储型（累积型）SiC-MISFET包括SiC衬底，n型漂移层，p型阱区，n型源区，含有n型杂质的SiC沟道层和 是存储型（堆积型）沟道层，与阱层接触的p型重掺杂接触层，栅极绝缘膜，栅电极。 存储型SiC-MISFET的特征在于，在形成前，通过将p导电型离子注入到n型漂移层的上表面部分中而形成的重掺杂层的浓度高于阱区中的浓度 的通道层。 平面栅极SiC-MISFET可以是垂直的或水平的。