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33 条记录 (耗时 0.015 秒)

    Field effect transistor and method of manufacturing the same
    2.
    发明公开
    Field effect transistor and method of manufacturing the same 审中-公开
    Feldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1143526A3

    公开(公告)日：2005-09-28

    申请号：EP01303280.0

    申请日：2001-04-06

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Yokogawa, Toshiya ,  Takahashi, Kunimasa ,  Kusumoto, Osamu

    IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/20 ,  H01L21/04 ,  H01L21/336

    CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

    摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate 11, an n-type semiconductor layer 12 formed on the n-type substrate 11, a p-type semiconductor layer 13 formed on the n-type semiconductor layer 12, a p-type region 14 embedded in the n-type semiconductor layer 12, an n-type region 15 embedded in the n-type semiconductor layer 12 and the p-type semiconductor layer 13, an n-type source region 16 disposed in the p-type semiconductor layer 13 on its surface side, an insulating layer 17 disposed on the p-type semiconductor layer 13, a gate electrode 18 disposed on the insulating layer 17, a source electrode 19, and a drain electrode 20. The n-type semiconductor layer 12, the p-type semiconductor layer 13, and the p-type region 14 are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.

    摘要翻译： 提供了具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底11，形成在n型衬底11上的n型半导体层12，形成在n型半导体层12上的p型半导体层13，p型区域 嵌入在n型半导体层12中的n型区域15，嵌入在n型半导体层12和p型半导体层13中的n型区域15，设置在p型半导体层 在绝缘层17上设置绝缘层17，设置在绝缘层17上的栅电极18，源电极19和漏电极20. n型半导体层12， p型半导体层13和p型区域14分别由具有至少2eV的带隙的宽间隙半导体制成。

    Silicon carbide semiconductor device and method for fabricating the same
    5.
    发明公开
    Silicon carbide semiconductor device and method for fabricating the same 有权
    Siliziumkarbidhalbleiterbauelement和Verfahren zu dessen Herstellung

    公开(公告)号：EP1460681A2

    公开(公告)日：2004-09-22

    申请号：EP04006581.5

    申请日：2004-03-18

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

    IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

    CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

    摘要翻译： 本发明的半导体器件具有：碳化硅衬底1; n型高电阻层2; 设置在高电阻层2的表面区域中的阱区域3; 设置在每个阱区域3内的p +接触区域4; 源区域5，其设置成横向围绕每个阱区域3内的p +接触区域4; 设置在源极区域5上并由镍制成的第一源电极8; 覆盖第一源电极8并由铝制成的第二源电极9; 设置在夹在两个阱区域3之间的高电阻层2的一部分上的栅极绝缘膜6; 由铝制成的栅电极10; 以及覆盖第二源电极9和栅电极10并由氧化硅制成的层间电介质膜11。

    Semiconductor element
    7.
    发明公开
    Semiconductor element 有权
    Halbleiterelement

    公开(公告)号：EP1204145A2

    公开(公告)日：2002-05-08

    申请号：EP01125141.0

    申请日：2001-10-23

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Kitabatake, Makoto

    IPC分类号： H01L27/07 ,  H01L27/095

    CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7806 ,  H01L29/8083

    摘要： The present invention provides a semiconductor element in which the field-effect transistor and the Schottky diode are arranged such that a depletion layer stemming from the Schottky diode is superimposed on a depletion layer stemming from a junction between a second conductivity type semiconductor constituting the field-effect transistor and a drift region (first conductivity type semiconductor) in an off-state. According to preferable embodiments of the present invention, the reverse recovery time due to a parasitic diode can be reduced by providing the Schottky diode such that the element area of the semiconductor element is not increased. Moreover, the breakdown voltage in the semiconductor element can be improved.

    摘要翻译： 本发明提供一种半导体元件，其中场效应晶体管和肖特基二极管被布置成使得源自肖特基二极管的耗尽层叠加在源于构成场效应晶体管的第二导电类型半导体之间的结的耗尽层上， 效应晶体管和漂移区域（第一导电型半导体）处于断开状态。 根据本发明的优选实施例，通过提供肖特基二极管使得半导体元件的元件面积不增加，可以减少由寄生二极管引起的反向恢复时间。 此外，可以提高半导体元件中的击穿电压。

    Insulated-gate semiconductor element and method for manufacturing the same
    8.
    发明公开
    Insulated-gate semiconductor element and method for manufacturing the same 有权
    HerstellungsverfahrenfürHalbleiterbauelement mit isoliertem Gate

    公开(公告)号：EP1032048A1

    公开(公告)日：2000-08-30

    申请号：EP00103360.4

    申请日：2000-02-22

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Takahashi, Kunimasa ,  Uenoyama, Takeshi

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L29/423 ,  H01L21/265

    CPC分类号： H01L29/7813 ,  H01L21/049 ,  H01L29/66068

    摘要： An insulated-gate semiconductor element having a high breakdown voltage is provided. The surface of a silicon carbide substrate is etched to form a concave portion. A particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. A gate electrode is formed on the oxide film. The oxide film at the bottom surface is thicker than at the side surfaces, so that a high breakdown voltage can be ensured, even when the surface of the silicon carbide layer is a face with which a superior epitaxial layer can be attained, such as the (111) Si-face of β -SiC or the (0001) Si-face of α -SiC.

    摘要翻译： 提供具有高击穿电压的绝缘栅半导体元件。 蚀刻碳化硅衬底的表面以形成凹部。 从上方照射粒子束，例如离子束，至少在凹部的底面形成有缺陷层。 在氧化气氛中加热基板，至少在凹部的侧面和底面形成氧化膜。 在氧化膜上形成栅电极。 底面的氧化膜比侧面厚，因此即使当碳化硅层的表面是能够获得优异的外延层的面时，也能够确保高的击穿电压，例如 （111）β-SiC的Si面或α-SiC的（0001）Si面。

    Method of fabricating semicondutor thin film and method of fabricating hall-effect device
    10.
    发明公开
    Method of fabricating semicondutor thin film and method of fabricating hall-effect device 失效
    一种用于制造半导体薄膜及其制造方法的霍尔效应器件的方法。

    公开(公告)号：EP0632485A3

    公开(公告)日：1995-08-23

    申请号：EP94108235.6

    申请日：1994-05-27

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kawasaki, Tetuo ,  Koretika, Tetuhiro ,  Kitabatake, Makoto ,  Hirao, Takashi

    IPC分类号： H01L21/20 ,  H01L43/14

    CPC分类号： H01L43/08 ,  H01L21/02381 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02549 ,  H01L21/02631 ,  H01L43/065 ,  Y10S438/974

    摘要： A method of fabricating a semiconductor thin film (4) is initiated with preparing a substrate (1) having a surface consisting of a single crystal of Si. The surface has an oxide film. Then, the oxide film is removed. The dangling bonds of the Si atoms on the surface are terminated with hydrogen atoms. An initial layer (2) is formed on the substrate of the single crystal of Si terminated with the hydrogen atoms, of at least one selected from the group consisting of Al, Ga, and In. A buffer layer (3) containing at least In and Sb is formed on the initial layer. A semiconductor thin film (4) containing at least In and Sb is formed on the buffer layer (3) at a temperature higher than the temperature at which the buffer layer (3) is started to be formed.
       There is also disclosed a method of fabricating a Hall-effect device. This method is initiated with forming a semiconductor thin film by making use of the above-described fabrication method. Then, electrodes are attached to the thin film.