公开(公告)号：EP1968104A2

公开(公告)日：2008-09-10

申请号：EP08011174.3

申请日：2003-07-09

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya c/o Matsushita Electric Industrial Co., Ltd ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L21/336 ,  H01L21/82 ,  H01L29/872 ,  H01L29/812 ,  H01L29/45 ,  H01L27/06 ,  H01L29/772

CPC分类号： H01L29/7813 ,  H01L21/0485 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931

摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

摘要翻译： 累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有形成在阱区103的表面区域上的多重掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 并且栅极电极110.累积沟道层104具有这样的结构，其中，在量子效应下允许载流子向未掺杂层104b扩展移动的未掺杂层104b和“掺杂层104a被交替堆叠。 提供源电极111，其进入累积沟道层104和接触区域105以与接触区域105直接接触。通过离子注入不需要形成源极区域，导致制造成本降低。

公开(公告)号：EP1460681A3

公开(公告)日：2007-11-28

申请号：EP04006581.5

申请日：2004-03-18

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

公开(公告)号：EP1460681A2

公开(公告)日：2004-09-22

申请号：EP04006581.5

申请日：2004-03-18

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L23/485

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7835 ,  H01L29/8083 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device is provided with: a silicon carbide substrate 1 ; an n-type high resistance layer 2 ; well regions 3 provided in a surface region of the high resistance layer 2 ; a p + contact region 4 provided within each well region 3 ; a source region 5 provided to laterally surround the p + contact region 4 within each well region 3 ; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3 ; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

摘要翻译： 本发明的半导体器件具有：碳化硅衬底1; n型高电阻层2; 设置在高电阻层2的表面区域中的阱区域3; 设置在每个阱区域3内的p +接触区域4; 源区域5，其设置成横向围绕每个阱区域3内的p +接触区域4; 设置在源极区域5上并由镍制成的第一源电极8; 覆盖第一源电极8并由铝制成的第二源电极9; 设置在夹在两个阱区域3之间的高电阻层2的一部分上的栅极绝缘膜6; 由铝制成的栅电极10; 以及覆盖第二源电极9和栅电极10并由氧化硅制成的层间电介质膜11。

公开(公告)号：EP1265295A2

公开(公告)日：2002-12-11

申请号：EP02012326.1

申请日：2002-06-04

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Uchida, Masao ,  Kitabatake, Makoto ,  Yokogawa, Toshiya ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Miyanaga, Ryoko ,  Yamashita, Kenya

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor substrate made of 4H-SiC, an epitaxially grown 4H-SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

公开(公告)号：EP1104031A3

公开(公告)日：2005-10-12

申请号：EP00124829.3

申请日：2000-11-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kidoguchi, Isao ,  Ishibashi, Akihiko ,  Miyanaga, Ryoko ,  Sugahara, Gaku ,  Suzuki, Masakatsu ,  Kume, Masahiro ,  Ban, Yuzaburo ,  Morita, Kiyoyuki ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki

IPC分类号： H01L21/20 ,  C30B29/40 ,  H01L33/00 ,  H01S5/323

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/405 ,  H01L33/46 ,  H01S5/2077 ,  H01S5/2201 ,  H01S5/32341 ,  H01S5/4031 ,  H01S2304/00

摘要： The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of Al u Ga v In w N, wherein 0 ≦ u, v, w ≦ 1 and u + v + w = 1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of Al x Ga y In z N, wherein 0 ≦ x, y, z ≦ 1 and x + y + z = 1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.

公开(公告)号：EP1220304A2

公开(公告)日：2002-07-03

申请号：EP01130923.4

申请日：2001-12-27

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Ishibashi, Akihiko ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki ,  Otsuka, Nobuyuki ,  Sugahara, Gaku ,  Miyanaga, Ryoko ,  Shimamoto, Toshitaka ,  Harafuji, Kenji ,  Ban, Yuzaburoji ,  Ohnaka, Kiyoshi

IPC分类号： H01L21/20 ,  H01L33/00

CPC分类号： H01L33/007 ,  B82Y20/00 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/0265 ,  H01L33/32 ,  H01S5/22 ,  H01S5/3063 ,  H01S5/3215 ,  H01S5/3216 ,  H01S5/34333 ,  H01S2304/04 ,  H01S2304/12

摘要： The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.

摘要翻译： 用于制造本发明的氮化物半导体的制造方法包括以下步骤：（1）生长通过在由第一III族氮化物衬底的第一半导体层供给的第一III族原料和含有氮的V族源; 和（2）生长通过提供一个第二III族原料和含有氮的V族原料制成的第二III族氮化物的第一半导体层上的第二半导体层。 至少以下步骤：（1）和（2）包括供应在所述衬底的p型掺杂剂的步骤，和在所述第一半导体层和第二半导体层之间的界面附近区域生长所以没有的密度一个 p型掺杂剂局部增加。

公开(公告)号：EP0952574A1

公开(公告)日：1999-10-27

申请号：EP99107567.2

申请日：1999-04-15

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kume, Masahiro ,  Ban, Yazuburo ,  Kidoguchi, Isao ,  Kamiyama, Satoshi ,  Tsujimura, Ayumu ,  Ishibashi, Akihiko ,  Hasegawa, Yoshiaki ,  Miyanaga, Ryoko

IPC分类号： G11B7/125 ,  G11B7/00

CPC分类号： G11B7/126 ,  G11B7/005 ,  G11B7/128 ,  G11B7/135 ,  G11B7/1369 ,  G11B11/10515 ,  G11B11/10543

摘要： Between a semiconductor laser diode (12) and an optical disk (11), a collimator lens (13) for collimating a laser beam output from the semiconductor laser diode, a liquid crystal optical shutter (14) for attenuating the collimated beam having passed through the collimator lens, and a beam splitter (15) for splitting reflected light from the optical disk are disposed. In addition, a collecting lens for collecting the collimated beam obtained by the collimator lens on a data holding surface of the optical disk (11) is further disposed.

摘要翻译： 在半导体激光二极管（12）和光盘（11）之间，用于准直从半导体激光二极管输出的激光束的准直透镜（13），用于衰减经过的准直光束的液晶光学快门（14） 准直透镜和用于分离来自光盘的反射光的分束器（15）。 此外，还设置有用于将由准直透镜获得的准直光束收集在光盘（11）的数据保持表面上的收集透镜。

公开(公告)号：EP1689000A1

公开(公告)日：2006-08-09

申请号：EP04819378.3

申请日：2004-11-24

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Uchida, Masao ,  Kitabatake, Makoto ,  Kusumoto, Osamu ,  Yamashita, Kenya ,  Takahashi, Kunimasa ,  Miyanaga, Ryoko

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction.
In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

摘要翻译： 在本发明的半导体器件中，形成在碳化硅衬底上的n型碳化硅层的顶表面从（0001）面向<11-20>方向错开。 栅电极，源电极等元件被布置成使得在通道区域中，主导电流沿着误差方向流动。 在本发明中，形成栅极绝缘膜，然后在含有V族元素的气氛中进行热处理。 以这种方式，碳化硅层和栅极绝缘膜之间的界面处的界面态密度降低。 结果，电子迁移率在错误方向A上比在与错误方向A垂直的方向上更高。

公开(公告)号：EP1523032A2

公开(公告)日：2005-04-13

申请号：EP04023713.3

申请日：2004-10-05

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Yamashita, Kenya ,  Kitabatake, Makoto ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Uchida, Masao ,  Miyanaga, Ryoko

IPC分类号： H01L21/04

CPC分类号： H01L29/518 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/7828

摘要： A gate insulating film which is an oxide layer mainly made of SiO 2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100°C and lower than 1250°C, whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

摘要翻译： 通过热氧化在碳化硅衬底上形成作为主要由SiO 2形成的氧化物层的栅极绝缘膜，然后将所得到的结构在室内的惰性气体气氛中进行退火。 此后，将碳化硅 - 氧化物层状结构放置在具有真空泵的室中，在高于1100℃且低于1250℃的高温下暴露于减压NO气体气氛中，从而在 栅极绝缘膜。 结果，得到作为含有氧化物层的V族元素的栅极绝缘膜，其下部具有高的氮浓度区域，其相对介电常数为3.0以上。 含V族元素的氧化物层和碳化硅层之间的界面区域的界面态密度降低。

公开(公告)号：EP0952645B1

公开(公告)日：2004-12-15

申请号：EP99107985.6

申请日：1999-04-22

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kamiyama, Satoshi ,  Kume, Masahiro ,  Miyanaga, Ryoko ,  Kidoguchi, Isao ,  Ban, Yuzaburo ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki ,  Ishibashi, Akihiko

IPC分类号： H01S5/32

CPC分类号： B82Y20/00 ,  H01S5/3054 ,  H01S5/3063 ,  H01S5/343 ,  H01S5/34333