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1.发明授权METHODS FOR FORMING INTEGRATED CIRCUIT STRUCTURES CONTAINING ENHANCED-SURFACE-AREA CONDUCTIVE LAYERS 有权与大内表面的导电层制造方法进行集成电路结构
公开(公告)号：EP1299901B1
公开(公告)日：2008-04-23
申请号：EP01942104.9
申请日：2001-06-07
IPC分类号： H01L21/02
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or 'islanded' surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate or a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
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公开(公告)号：EP1212476B1
公开(公告)日：2004-11-03
申请号：EP00959525.7
申请日：2000-08-28
发明人： BASCERI, Cem , GEALY, Dan
IPC分类号： C23C16/40 , H01L21/316 , H01L21/02 , H01G4/12 , H01B3/12 , C04B35/468 , C04B35/47 , C04B35/472
CPC分类号： H01L28/56 , C23C16/409 , H01L21/31691
摘要： The present invention provides a method for forming a dielectric film, e.g., a barium-strontium-titanate film, preferably having a thickness of less than about 600 Å. According to the present invention, the dielectric film is preferably formed using a chemical vapor deposition process in which an interfacial layer and a bulk layer are formed. The interfacial layer has an atomic percent of titanium less than or equal to the atomic percent of titanium in the bulk layer. Such films are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.
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3.发明授权MICROFEATURE WORKPIECE PROCESSING APPARATUS AND METHODS FOR BATCH DEPOSITION OF MATERIALS ON MICROFEATURE WORKPIECES 有权处理装置用于微结构特征具有分离材料对微观结构的特征是包含WORKPIECES充电模式组件和方法
公开(公告)号：EP1660698B1
公开(公告)日：2008-06-04
申请号：EP04781653.3
申请日：2004-08-18
发明人： ZHENG, Lingyi, A. , DOAN, Trung, T. , BREINER, Lyle, D. , PING, Er-Xuan , WEIMER, Ronald, A. , KUBISTA, David, J. , BEAMAN, Kevin, L. , BASCERI, Cem
IPC分类号： C23C16/458
CPC分类号： C23C16/4583 , C23C16/45546 , C23C16/45578 , Y10S206/832
摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.
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公开(公告)号：EP1532292B1
公开(公告)日：2007-06-27
申请号：EP03771691.7
申请日：2003-07-21
CPC分类号： C30B25/14 , C23C14/0641 , C23C14/081 , C23C16/34 , C23C16/403 , C23C16/45527 , C23C16/45531
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
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5.发明公开GATED FIELD EFFECT DEVICES AND METHODS OF FORMING A GATED FIELD EFFECT DEVICE 有权盖茨场效应器件中，生成GATES场效应元素的方法
公开(公告)号：EP1759415A2
公开(公告)日：2007-03-07
申请号：EP05756010.4
申请日：2005-05-31
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
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6.发明公开
公开(公告)号：EP1297562A2
公开(公告)日：2003-04-02
申请号：EP01942105.6
申请日：2001-06-07
发明人： AGARWAL, Vishnu, K. , DERDERIAN, Garo , SANDHU, Gurtej, S. , LI, Weimin, M. , VISOKAY, Mark , BASCERI, Cem , YANG, Sam
IPC分类号： H01L21/02
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500 °C and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Anstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as a first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
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7.发明公开DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES 审中-公开器件，系统和方法用于去除半导体器件寄生LINES
公开(公告)号：EP2904642A1
公开(公告)日：2015-08-12
申请号：EP13843408.9
申请日：2013-09-23
IPC分类号： H01L29/778
CPC分类号： H01L29/42316 , H01L29/0603 , H01L29/2003 , H01L29/205 , H01L29/4175 , H01L29/7786 , H01L29/7787 , H01L2224/16227
摘要： Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.
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8.发明公开MICROFEATURE WORKPIECE PROCESSING APPARATUS AND METHODS FOR BATCH DEPOSITION OF MATERIALS ON MICROFEATURE WORKPIECES 有权处理装置用于微结构特征具有分离材料对微观结构的特征是包含WORKPIECES充电模式组件和方法
公开(公告)号：EP1660698A1
公开(公告)日：2006-05-31
申请号：EP04781653.3
申请日：2004-08-18
发明人： ZHENG, Lingyi, A. , DOAN, Trung, T. , BREINER, Lyle, D. , PING, Er-Xuan , WEIMER, Ronald, A. , KUBISTA, David, J. , BEAMAN, Kevin, L. , BASCERI, Cem
IPC分类号： C23C16/458
CPC分类号： C23C16/4583 , C23C16/45546 , C23C16/45578 , Y10S206/832
摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.
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公开(公告)号：EP1623453A2
公开(公告)日：2006-02-08
申请号：EP04751377.5
申请日：2004-05-04
IPC分类号： H01L21/02
CPC分类号： H01L27/10855 , H01L27/10852 , H01L28/40 , H01L28/57
摘要： The invention includes methods in which metal oxide dielectric materials (50) are deposited over barrier layers (48). The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
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10.发明公开
公开(公告)号：EP1166338A1
公开(公告)日：2002-01-02
申请号：EP00917658.7
申请日：2000-02-23
IPC分类号： H01L21/02
CPC分类号： H01L28/55 , H01L21/31155 , H01L21/31691
摘要： A method for ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with donor dopants to reduce film leakage and improve resistance degradation of the BST film. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. The invention also relates to integrated circuits having a doped thin film high dielectric material used as an insulating layer in a capacitor structure.
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