公开(公告)号：EP1231825A4

公开(公告)日：2005-09-28

申请号：EP00940884

申请日：2000-06-29

申请人： MITSUBISHI ELECTRIC CORP

发明人： KATSURA TAKATOSHI ,  ITOH KENJI ,  NAGANO HIROAKI ,  ISOTA YOUJI ,  SHIMOZAWA MITSUHIRO ,  TAKAGI TADASHI ,  SUEMATSU NORIHARU ,  ONO MASAYOSHI ,  MAEDA KENICHI

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/538 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H03H3/00 ,  H03H7/01 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K9/00 ,  H05K3/46 ,  H01L25/00 ,  H03D7/00

CPC分类号： H05K1/0216 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/552 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/3011 ,  H03H3/00 ,  H03H7/01 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/141 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09972 ,  H01L2924/00

摘要： A multilayer substrate module to which an external ground node (20) supplies a reference ground potential (Vss) includes a plurality of ground lines (170-1, 170-2, 170-3), which correspond to a plurality of internal circuits (210, 220, 230), respectively. A common node (Ncmn) for joining the ground lines (170-1, 170-2, 170-3) is provided in an insulating layer (105C) in the multilayer substrate module. The common node (Ncmn) is coupled electrically to the ground node (20) through a ground pin terminal (204) shared among the internal circuits (210, 220, 230). The common node (Ncmn) is provided preferably in the lowermost insulating layer in the multilayer substrate module (120). The parasitic inductance appearing in a ground current path and shared among the internal circuits (210, 220, 230) can be decreased using fewer ground pin terminals. Therefore, the ground current path is prevented from being circuitous among the internal circuits (210, 220, 23O), resulting in stabilized operation.

公开(公告)号：EP1111773A4

公开(公告)日：2002-11-20

申请号：EP99973947

申请日：1999-06-29

申请人： MITSUBISHI ELECTRIC CORP

发明人： SUEMATSU NORIHARU ,  ONO MASAYOSHI ,  TAKAGI TADASHI

IPC分类号： H03D7/14

CPC分类号： H03D7/1433 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475

摘要： A semiconductor circuit comprises a pair of transistors (11, 12) connected commonly at their collectors and emitters having their bases for receiving a first signal and its inverted signal, respectively; a transistor (13) connected between the common emitters and the ground potential and having a base for receiving a second signal; and an output circuit having an output load (51) connected between the common collector and a supply voltage (Vcc) to receive a third signal from the common collector. For low-voltage operation, the semiconductor circuit suppresses generation of even harmonics of a local oscillation signal.