公开(公告)号：EP1312120A1

公开(公告)日：2003-05-21

申请号：EP01965876.4

申请日：2001-08-13

申请人： Matrix Semiconductor, Inc.

发明人： LEE, Thomas, H. ,  SUBRAMANIAN, Vivek ,  CLEEVES, James, M. ,  WALKER, Andrew, J. ,  PETTI, Christopher ,  KOUZNETZOV, Igor, G. ,  JOHNSON, Mark, G. ,  FARMWALD, Paul, M. ,  HERNER, Brad

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L27/14 ,  G11C11/34 ,  H01L21/8246 ,  H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。

公开(公告)号：EP1141963A1

公开(公告)日：2001-10-10

申请号：EP99921564.3

申请日：1999-04-29

申请人： Matrix Semiconductor, Inc.

发明人： JOHNSON, Mark, G. ,  LEE, Thomas, H. ,  SUBRAMANIAN, Vivek ,  FARMWALD, P., Michael ,  CLEEVES, James, M.

IPC分类号： G11C13/00 ,  G11C11/22 ,  G11C17/00

CPC分类号： H01L27/1021 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/76

摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers (51a1, 51a2, 51b2), each layer (51a1) of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.