公开(公告)号：EP4293821A3

公开(公告)日：2024-05-22

申请号：EP23208234.7

申请日：2018-05-24

申请人： MediaTek Inc.

发明人： HAN, Fu-Yi ,  CHOU, Che-Ya ,  KUO, Che-Hung ,  WU, Wen-Chou ,  CHEN, Nan-Cheng ,  LIN, Min-Chen ,  LIU, Hsing-Chih

IPC分类号： H01L23/66 ,  H01Q21/06 ,  H01Q1/22

CPC分类号： H01L23/66 ,  H01L2223/661620130101 ,  H01L2223/667720130101 ,  H01L2224/0410520130101 ,  H01L2224/1210520130101 ,  H01L2224/1314420130101 ,  H01L2224/1314720130101 ,  H01L2224/1622720130101 ,  H01L2224/4822720130101 ,  H01L2225/102320130101 ,  H01L2225/103520130101 ,  H01L2225/105820130101 ,  H01L2924/1519220130101 ,  H01L2924/1531120130101 ,  H01L2924/1532120130101 ,  H01L24/20 ,  H01L24/16 ,  H01L2224/1623520130101 ,  H01L2924/1533120130101 ,  H01Q1/2283 ,  H01L23/5389 ,  H01L23/49816 ,  H01L23/5384 ,  H01Q21/06 ,  H01L23/49822 ,  H01L23/49827

摘要： One embodiment of the present disclosure provides a semiconductor package including a bottom chip package (10) having a first side (10a) and a second side (10b) opposing the first side (10a) , and a top antenna package (20) mounted on the first side (10a) of the bottom chip package (10). The bottom chip package (10) further includes a semiconductor chip (30). The semiconductor chip (30) may include a RFIC chip. The top antenna package (20) has at least one radiative antenna element (220).

公开(公告)号：EP3582260A3

公开(公告)日：2020-01-22

申请号：EP19172944.1

申请日：2019-05-07

申请人： MediaTek Inc.

发明人： LIN, Min-Chen ,  LEE, Yi-Hui ,  CHOU, Che-Ya ,  CHEN, Nan-Cheng

IPC分类号： H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L25/065

摘要： An electronic package (1) configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package (1) includes a package substrate (20) of a rectangular shape. A chip package (10) having a first high-speed interface circuit die (11) is mounted on a top surface (201) of the package substrate (20) . The chip package (10) is rotated relative to the package substrate (20) above a vertical axis (Z) that is orthogonal to the top surface (201) through about 45 degrees. The first high-speed interface circuit die (11) includes a first Serializer/Deserializer, SerDes, circuit block.

公开(公告)号：EP3273475A2

公开(公告)日：2018-01-24

申请号：EP17173260.5

申请日：2017-05-29

申请人： MediaTek Inc.

发明人： LIN, Min-Chen ,  CHOU, Che-Ya ,  CHEN, Nan-Cheng

IPC分类号： H01L23/552 ,  H01L23/66 ,  H01L23/538

CPC分类号： H01L23/5386 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/37001

摘要： A semiconductor package structure including a redistribution layer (RDL) structure (110) having a first surface (101) and a second surface (103) opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer (100a, 100b) and a first conductive layer (102) disposed at a first layer-level of the IMD layer. A molding compound (150) covers the first surface of the RDL structure. A first semiconductor die (120) is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures (160) is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

公开(公告)号：EP4293821A2

公开(公告)日：2023-12-20

申请号：EP23208234.7

申请日：2018-05-24

申请人： MediaTek Inc.

发明人： HAN, Fu-Yi ,  CHOU, Che-Ya ,  KUO, Che-Hung ,  WU, Wen-Chou ,  CHEN, Nan-Cheng ,  LIN, Min-Chen ,  LIU, Hsing-Chih

IPC分类号： H01Q1/22

摘要： One embodiment of the present disclosure provides a semiconductor package including a bottom chip package (10) having a first side (10a) and a second side (10b) opposing the first side (10a) , and a top antenna package (20) mounted on the first side (10a) of the bottom chip package (10). The bottom chip package (10) further includes a semiconductor chip (30). The semiconductor chip (30) may include a RFIC chip. The top antenna package (20) has at least one radiative antenna element (220).

公开(公告)号：EP3582260A2

公开(公告)日：2019-12-18

申请号：EP19172944.1

申请日：2019-05-07

申请人： MediaTek Inc.

发明人： LIN, Min-Chen ,  LEE, Yi-Hui ,  CHOU, Che-Ya ,  CHEN, Nan-Cheng

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L25/065

摘要： An electronic package (1) configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package (1) includes a package substrate (20) of a rectangular shape. A chip package (10) having a first high-speed interface circuit die (11) is mounted on a top surface (201) of the package substrate (20) . The chip package (10) is rotated relative to the package substrate (20) above a vertical axis (Z) that is orthogonal to the top surface (201) through about 45 degrees. The first high-speed interface circuit die (11) includes a first Serializer/Deserializer, SerDes, circuit block.

公开(公告)号：EP3273475A3

公开(公告)日：2018-05-16

申请号：EP17173260.5

申请日：2017-05-29

申请人： MediaTek Inc.

发明人： LIN, Min-Chen ,  CHOU, Che-Ya ,  CHEN, Nan-Cheng

IPC分类号： H01L23/552 ,  H01L23/66 ,  H01L23/538

CPC分类号： H01L23/5386 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/37001

摘要： A semiconductor package structure including a redistribution layer (RDL) structure (110) having a first surface (101) and a second surface (103) opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer (100a, 100b) and a first conductive layer (102) disposed at a first layer-level of the IMD layer. A molding compound (150) covers the first surface of the RDL structure. A first semiconductor die (120) is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures (160) is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

摘要翻译： 提供了包括具有第一表面（101）和与其相对的第二表面（103）的再分布层（RDL）结构（110）的半导体封装结构。 RDL结构包括设置在IMD层的第一层级的金属间介电（IMD）层（100a，100b）和第一导电层（102）。 模塑料（150）覆盖RDL结构的第一表面。 第一半导体管芯（120）设置在RDL结构的第二表面之上并电耦合到RDL结构。 多个凸块结构（160）设置在RDL结构的第二表面之上并电耦合到RDL结构。