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1.发明公开CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES AND MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT 审中-公开TAKTWIEDERGABE-和时序方法在多设备和多内存控制器具有灵活的数据对齐系统
公开(公告)号：EP2220766A1
公开(公告)日：2010-08-25
申请号：EP08861510.9
申请日：2008-12-04
CPC分类号： G06F1/10 , G11C5/025 , G11C7/02 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/20 , G11C7/22 , G11C7/222 , H01L25/0657 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H04L7/0008 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.
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2.发明公开AN APPARATUS AND A METHOD OF PRODUCING A BOOSTED VOLTAGE USING A PLURALITY OF CHARGE PUMP CIRCUITS 有权用于产生电压的装置和方法推动使用多条充电泵激电路
公开(公告)号：EP2195913A1
公开(公告)日：2010-06-16
申请号：EP08800289.4
申请日：2008-09-09
发明人： PYEON, Hong, Beom
IPC分类号： H02M3/07 , G11C11/4063 , G11C7/12
CPC分类号： G11C11/4074 , G11C5/145 , G11C11/406 , G11C11/4076 , G11C2211/4061 , G11C2211/4067 , G11C2211/4068 , H02M3/073 , H02M2003/077
摘要： An apparatus and a method for producing a boosted voltage using a plurality of charge pumps circuits, charge pump control signals and an active capacitive element of an active charge pump, wherein the capacitive element of the activated charge pump is charged in response to the input voltage to the charge pump and the charge pump signal.
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公开(公告)号：EP2126918A1
公开(公告)日：2009-12-02
申请号：EP07855602.4
申请日：2007-12-21
发明人： PYEON, Hong, Beom , OH, HakJune , KIM, Jin-Ki
CPC分类号： G06F13/4022 , G11C7/1048 , G11C7/18 , G11C11/408
摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
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公开(公告)号：EP1929480A1
公开(公告)日：2008-06-11
申请号：EP06790771.7
申请日：2006-09-29
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C7/10 , G11C11/4197 , G11C16/06
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
摘要： A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.
摘要翻译： 串联耦合设备的技术，采用菊花链级联布置。 设备以菊花链级联布置耦合，使得第一设备的输出在菊花链中稍后耦合到第二设备的输入以适应信息（诸如数据，地址和命令信息以及控制信号）向 来自第一设备的第二设备。 耦合在菊花链中的器件包括串行输入（SI）和串行输出（SO）。 信息通过SI输入到设备。 信息通过SO从设备输出。 菊花链级联中的较早器件的SO在菊花链级联中稍后与器件的SI相耦合。 通过设备的SI输入到较早设备的信息通过设备并通过设备的SO从设备输出。 然后通过来自早期设备的SO和后面的设备的SI的连接将信息传送到更晚的设备的SI。
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5.发明公开A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 审中-公开与桥设备的复合存储于连接分立存储装置WITH A SYSTEM
公开(公告)号：EP2345035A1
公开(公告)日：2011-07-20
申请号：EP09820146.0
申请日：2009-10-14
发明人： KIM, Jin-Ki , PYEON, Hong, Beom
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
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公开(公告)号：EP1932158A1
公开(公告)日：2008-06-18
申请号：EP06790773.3
申请日：2006-09-29
发明人： OH, HakJune , PYEON, Hong, Beom , KIM, Jin-Ki
IPC分类号： G11C11/4197 , G11C11/4093 , G11C11/4063 , G11C16/26
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译： 公开了一种用于控制对半导体存储器中的串行数据链路接口的输出端口的数据传输的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使存储器件能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储器组，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。
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7.发明授权APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA 有权设备和页编程操作与镜像备份数据存储器安排方法
公开(公告)号：EP2118901B1
公开(公告)日：2013-09-18
申请号：EP08714596.7
申请日：2008-02-13
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
CPC分类号： G06F13/4243 , G06F13/4247
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8.发明授权
公开(公告)号：EP1932157B1
公开(公告)日：2011-11-09
申请号：EP06790770.9
申请日：2006-09-29
发明人： KIM, Jin-Ki , PYEON, Hong, Beom
IPC分类号： G11C11/4193 , G11C11/4197 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译： 公开了一种用于控制对半导体存储器中的串行数据链路接口的输出端口的数据传输的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使存储器件能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储器组，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。
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9.发明公开APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA 有权设备和页编程操作与镜像备份数据存储器安排方法
公开(公告)号：EP2118901A1
公开(公告)日：2009-11-18
申请号：EP08714596.7
申请日：2008-02-13
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
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10.发明公开METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE 审中-公开方法KONFIGUIEREN的非易失性存储器，用于混合动力驱动
公开(公告)号：EP2035935A1
公开(公告)日：2009-03-18
申请号：EP07763834.4
申请日：2007-06-29
发明人： PYEON, Hong, Beom , OH, HakJune
CPC分类号： G06F9/4408 , G06F3/061 , G06F3/0625 , G06F3/0664 , G06F3/068 , G06F12/0866 , G06F2212/222 , Y02D10/154
摘要： A method is provided to operate a non-volatile memory (NVM) in a hybrid drive mode in response to a user selection. To operate in hybrid drive mode, a computer operating system and a basic input/output system are preferably updated to identify the NVM as part of the same logical bootable disk, or logical hybrid drive, as a hard disk drive. Bootable disk sector and address mapping can be modified to reflect the addition or removal of the NVM. The NVM is preferably user-replaceable and upgradeable without opening the computer's casing. When the NVM includes more than one NVM module, a first NVM module can operate in hybrid disk mode while a second NVM module operates in a normal storage mode. Since no internal hardware modification is required, this approach can provide hybrid disk performance using conventional hardware, or to enhance performance of an existing hybrid drive.
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