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1.发明授权Method in a microprocessor with hardware controlled power management and selectable input/output control pins 失效在与硬件控制电源管理和可选的输入输出控制插头插脚的微处理器的方法
公开(公告)号：EP1241555B1
公开(公告)日：2004-05-26
申请号：EP02077209.1
申请日：1993-03-26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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公开(公告)号：EP0651331B1
公开(公告)日：2002-01-09
申请号：EP94307580.4
申请日：1994-10-17
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/30061 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04 , G06F12/0855
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公开(公告)号：EP0649083B1
公开(公告)日：2000-07-19
申请号：EP94307581.2
申请日：1994-10-17
发明人： Bluhm, Mark , Hervin, Mark W. , McMahan, Steven C. , Garibay, Raul A. Jr. , Eitrheim, John K. , McMahon, Ronald S.
CPC分类号： G06F9/30167 , G06F9/261 , G06F9/265 , G06F9/28 , G06F9/30145
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4.发明公开Microprocessor with hardware controlled power management and selectable input/output control pins 失效在与硬件控制电源管理和可选的输入输出控制插头插脚的微处理器的方法
公开(公告)号：EP1241555A2
公开(公告)日：2002-09-18
申请号：EP02077209.1
申请日：1993-03-26
IPC分类号： G06F1/32
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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5.发明授权Microprocessor comprising region configuration system and method for controlling memory subsystem operations by address region 失效微处理器的地址空间配置的系统，并通过地址范围来控制存储器系统的操作的方法
公开(公告)号：EP0598570B1
公开(公告)日：2000-01-19
申请号：EP93309081.3
申请日：1993-11-12
发明人： Bluhm, Mark , Garibay, JR. Raul A , Duschatko, Douglas Ewing , Herubin, Margaret R. , Martinez, Marvin Wayne Jr. , Quattromani, Marc A.
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0888
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6.发明授权Microprocessor with hardware controlled power management and selectable input/output control pins and method therfor 失效微处理器与硬件控制电源管理和可选的输入/输出控制管脚及其方法
公开(公告)号：EP1237066B1
公开(公告)日：2004-03-03
申请号：EP02077210.9
申请日：1993-03-26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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7.发明公开Microprocessor with hardware controlled power management and selectable input/output control pins 失效微处理器与硬件控制电源管理和可选的输入/输出控制插头插脚
公开(公告)号：EP1237066A3
公开(公告)日：2002-09-25
申请号：EP02077210.9
申请日：1993-03-26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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公开(公告)号：EP0649086B1
公开(公告)日：2000-07-19
申请号：EP94307584.6
申请日：1994-10-17
发明人： Bluhm, Mark , Garibay, Raul A , Jr , McMahan, Steven C. , Lie, Milton , Quattromani, Marc A. , Hervin, Mark W.
IPC分类号： G06F9/38
CPC分类号： G06F9/30061 , G06F9/3842 , G06F9/3863
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9.发明授权Microprocessor with hardware controlled power management and selectable input/output control pins and method therefor 失效微处理器与硬件控制电源管理和可选的输入/输出控制管脚及其方法
公开(公告)号：EP0828212B1
公开(公告)日：2008-07-16
申请号：EP97202844.3
申请日：1993-03-26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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10.发明公开Microprocessor with hardware controlled power management and selectable input/output control pins 失效微处理器与硬件控制电源管理和可选的输入输出控制插头插脚
公开(公告)号：EP1241555A3
公开(公告)日：2002-09-25
申请号：EP02077209.1
申请日：1993-03-26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/30079 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
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