Abstract:
A method for fabricating an integrated circuit comprising: fabricating a first portion of an active circuit area and an associated metal pad on a base substrate; depositing a passivation layer above the first portion of the active circuit area and above the metal pad, wherein at least portions of an upper surface of the passivation layer is nonplanar; etching at least one via through the passivation layer to the metal pad; etching a metal layer pattern into the passivation layer; and depositing a metal layer onto the metal layer pattern in the passivation layer to form a redistribution metal layer
Abstract:
The invention comprises a lid that is capable of being placed in contact with and attached to an integrated circuit that has an exposed surface of an integrated circuit die. The lid has portions that form a cavity between a surface of the lid and the exposed surface of the integrated circuit die when the lid is placed in contact with the integrated circuit. The lid also has portions that form a first fluid conduit for transporting a fluid into the cavity and a second fluid conduit for transporting the fluid out of the cavity. Heat from the integrated circuit die is absorbed by the fluid by direct convection and removed from the integrated circuit when the fluid is removed from the cavity.
Abstract:
A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.
Abstract:
A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.
Abstract:
Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed.
Abstract:
An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.
Abstract:
A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.
Abstract:
A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.
Abstract:
A method for fabricating an integrated circuit comprising: fabricating a first portion of an active circuit area and an associated metal pad on a base substrate; depositing a passivation layer above the first portion of the active circuit area and above the metal pad, wherein at least portions of an upper surface of the passivation layer is nonplanar; etching at least one via through the passivation layer to the metal pad; etching a metal layer pattern into the passivation layer; and depositing a metal layer onto the metal layer pattern in the passivation layer to form a redistribution metal layer