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公开(公告)号：EP3817055A1
公开(公告)日：2021-05-05
申请号：EP20174720.1
申请日：2020-05-14
发明人： WANG, Hui-Lin , HSU, Po-Kai , JHANG, Jing-Yin , CHEN, Hung-Yueh , WANG, Yu-Ping , WU, Jia-Rong , HUANG, Rai-Min , TSAI, Ya-Huei , CHANG, I-Fan
IPC分类号： H01L27/22
摘要： The disclosed MRAM device includes an array of magnetic tunneling junction (MTJ) elements on a substrate (12), wherein a dummy MTJ (46, 50) in which a bottom surface thereof is not connected to any metal is arranged between a first MTJ (44, 52) and a second MTJ (48). In an alternative arrangement two adjacent MTJs are placed between two dummy MTJs. Preferably, the device further includes metal interconnections (42) under the first and second MTJs, and an inter-metal dielectric layer (40) around the metal interconnections and directly under the dummy MTJ(s).
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公开(公告)号：EP3905250A1
公开(公告)日：2021-11-03
申请号：EP20184796.9
申请日：2020-07-08
发明人： WANG, Hui-Lin , HSU, Po-Kai , JHANG, Jing-Yin , WANG, Yu-Ping , CHEN, Hung-Yueh , CHEN, Wei
摘要： A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：EP3790064A1
公开(公告)日：2021-03-10
申请号：EP20174589.0
申请日：2020-05-14
发明人： WANG, Hui-Lin , HSU, Po-Kai , WENG, Chen-Yi , JHANG, Jing-Yin , WANG, Yu-Ping , CHEN, Hung-Yueh
摘要： A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
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公开(公告)号：EP3790011A1
公开(公告)日：2021-03-10
申请号：EP20174580.9
申请日：2020-05-14
发明人： WANG, Hui-Lin , WANG, Yu-Ping , WENG, Chen-Yi , HSIEH, Chin-Yang , TSAI, Si-Han , CHANG, Che-Wei , JHANG, Jing-Yin
摘要： A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：EP4202931A1
公开(公告)日：2023-06-28
申请号：EP23151392.0
申请日：2020-05-14
发明人： WANG, Hui-Lin , HSU, Po-Kai , WENG, Chen-Yi , JHANG, Jing-Yin , WANG, Yu-Ping , CHEN, Hung-Yueh
摘要： A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
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公开(公告)号：EP4057365A3
公开(公告)日：2022-11-30
申请号：EP22170649.2
申请日：2020-04-14
发明人： WANG, Hui-Lin , WANG, Yu-Ping , WENG, Chen-Yi , HSIEH, Chin-Yang , LEE, Yi-Hui , LIU, Ying-Cheng , SHIH, Yi-An , TSENG, I-Ming , JHANG, Jing-Yin , LIN, Chien-Ting
摘要： A semiconductor structure, comprising: a substrate having a memory device region and a logic device region; a first dielectric layer on the substrate; a plurality of memory stack structures on the first dielectric layer on the memory device region; a single insulating layer continuously and conformally covering the memory stack structures and the first dielectric layer, wherein the single insulating layer directly contacts top surfaces and sidewalls of the memory stack structures, and a thickness of the single insulating layer on top surfaces of the memory stack structures is smaller than a thickness of the single insulating layer on sidewalls of the memory stack structures; a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures; a third dielectric layer on the second dielectric layer; and a plurality of top vias formed in the third dielectric layer and respectively aligned to one of the memory stack structures, wherein the top vias penetrate the insulating layer on the top surfaces of the memory stack structures to directly contacting the memory stack structures.
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公开(公告)号：EP4057365A2
公开(公告)日：2022-09-14
申请号：EP22170649.2
申请日：2020-04-14
发明人： WANG, Hui-Lin , WANG, Yu-Ping , WENG, Chen-Yi , HSIEH, Chin-Yang , LEE, Yi-Hui , LIU, Ying-Cheng , SHIH, Yi-An , TSENG, I-Ming , JHANG, Jing-Yin , LIN, Chien-Ting
摘要： A semiconductor structure, comprising: a substrate having a memory device region and a logic device region; a first dielectric layer on the substrate; a plurality of memory stack structures on the first dielectric layer on the memory device region; a single insulating layer continuously and conformally covering the memory stack structures and the first dielectric layer, wherein the single insulating layer directly contacts top surfaces and sidewalls of the memory stack structures, and a thickness of the single insulating layer on top surfaces of the memory stack structures is smaller than a thickness of the single insulating layer on sidewalls of the memory stack structures; a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures; a third dielectric layer on the second dielectric layer; and a plurality of top vias formed in the third dielectric layer and respectively aligned to one of the memory stack structures, wherein the top vias penetrate the insulating layer on the top surfaces of the memory stack structures to directly contacting the memory stack structures.
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公开(公告)号：EP3772117A1
公开(公告)日：2021-02-03
申请号：EP20169339.7
申请日：2020-04-14
发明人： WANG, Hui-Lin , WANG, Yu-Ping , WENG, Chen-Yi , HSIEH, Chin-Yang , LEE, Yi-Hui , LIU, Ying-Cheng , SHIH, Yi-An , TSENG, I-Ming , JHANG, Jing-Yin , LIN, Chien-Ting
摘要： A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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