公开(公告)号：EP0902968A1

公开(公告)日：1999-03-24

申请号：EP97945682.0

申请日：1997-11-26

申请人： MITEL CORPORATION

发明人： OUELLET, Luc ,  TREMBLAY, Yves ,  GENDRON, Luc

IPC分类号： H01L21

CPC分类号： H01L21/76846 ,  H01L21/76856

摘要： A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.

公开(公告)号：EP0899868A1

公开(公告)日：1999-03-03

申请号：EP98306821.4

申请日：1998-08-26

申请人： MITEL CORPORATION

发明人： Manku, Tajinder ,  MacEachern, Leonard

IPC分类号： H03D7/00

CPC分类号： H03D7/00

摘要： A method of performing a frequency conversion of a radio frequency (RF) information signal by mixing the information signal with a modulated signal from local oscillator. The local oscillator signal is modulated with a periodic, coded or pseudo-random modulating signal. A system for generating an intermediate frequency (IF) output signal from the information signal is also provided.

摘要翻译： 通过将信息信号与来自本地振荡器的调制信号混合来执行射频（RF）信息信号的频率转换的方法。 本地振荡器信号用周期性，编码或伪随机调制信号进行调制。 还提供了一种用于从信息信号产生中频（IF）输出信号的系统。

公开(公告)号：EP0772912B1

公开(公告)日：1998-05-27

申请号：EP95929688.0

申请日：1995-07-20

申请人： MITEL CORPORATION

发明人： WIECZORKIEWICZ, Jerzy ,  SHETTY, Krishna ,  KENNEY, Terry ,  VAN DER VALK, Robert, L. ,  SPIJKER, Menno, T.

IPC分类号： H03L7/099 ,  H03L7/081 ,  G06F1/02

CPC分类号： H03L7/081

公开(公告)号：EP0817528A2

公开(公告)日：1998-01-07

申请号：EP97304489.4

申请日：1997-06-25

申请人： MITEL CORPORATION

发明人： Peres, Mauricio ,  Salemi, Hojjat

IPC分类号： H04Q11/08

CPC分类号： H04Q11/08

摘要： A digital switch array, comprises a serial input bus providing a plurality of input streams (2a, 2b) each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams (3a, 3b), each defining a plurality of time division multiplexed output channels, and an array of digital switches (1a, 1b, 1c, 1d) arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches (1a, 1b, 1c, 1d) are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device (9, 10) for each output timeslot so that when the enabling device (9, 10) is enabled the associated output timeslot is driven, and at least first and second enabling inputs (4a, 4b) which when simultaneously activated cause the enabling means to become enabled. An array of activation lines (5a, 5b, 6a, 6b) are arranged in rows and columns. The respective rows (5a, 5b) of activation lines are connected to the first enabling inputs (4a) of each row of the digital switches (1a, 1b, 1c, 1d) and the respective columns (6a, 6b) of activation lines are connected to the second enabling inputs (4b) of each column of the digital switches (la, 1b, 1c, 1d). A selected row (5a, 5b) and column (6a, 6b) of the activation lines can be simultaneously activated so that the enabling device (9, 10) of the digital switch (1a, 1b, 1c, 1d) whose first input is connected to the activated row (5a, 5b) and whose second input is connected to the activated column (6a, 6b) becomes enabled.

摘要翻译： 数字开关阵列包括提供多个输入流（2a，2b）的串行输入总线，每个输入流定义多个时分多路复用输入通道，串行输出总线提供多个输出流（3a，3b），每个定义 多个时分复用输出通道，以及排列成行和列的数字开关（1a，1b，1c，1d）阵列。 每行连接到相应的输入流组，并且每列连接到相应的输出流组。 数字开关（1a，1b，1c，1d）能够在任何输入和任何输出通道之间执行时隙交换。 每个数字开关包括用于每个输出时隙的使能装置（9,10），使得当使能装置（9,10）被使能时，相关联的输出时隙被驱动，并且至少第一和第二使能输入（4a，4b） 当同时激活时，使启用手段成为启用状态。 激活线阵列（5a，5b，6a，6b）以行和列排列。 激活线的相应行（5a，5b）连接到每行数字开关（1a，1b，1c，1d）的第一使能输入（4a），并且激活线的相应列（6a，6b） 连接到数字开关（1a，1b，1c，1d）的每列的第二使能输入（4b）。 可以同时激活激活线的选定行（5a，5b）和列（6a，6b），使得其第一输入的数字开关（1a，1b，1c，1d）的使能装置（9,10） 连接到激活的行（5a，5b）并且其第二输入连接到激活的列（6a，6b）变得有效。

公开(公告)号：EP0772912A2

公开(公告)日：1997-05-14

申请号：EP95929688.0

申请日：1995-07-20

申请人： MITEL CORPORATION

发明人： WIECZORKIEWICZ, Jerzy ,  SHETTY, Krishna ,  KENNEY, Terry ,  VAN DER VALK, Robert, L. ,  SPIJKER, Menno, T.

IPC分类号： H03L7

CPC分类号： H03L7/081

摘要： A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.

公开(公告)号：EP0598795A1

公开(公告)日：1994-06-01

申请号：EP92917204.0

申请日：1992-08-10

申请人： MITEL CORPORATION

发明人： OUELLET, Luc

IPC分类号： H01L21 ,  H01L23

CPC分类号： H01L21/02142 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/3121 ,  H01L23/296 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： PCT No. PCT/CA92/00346 Sec. 371 Date Feb. 23, 1994 Sec. 102(e) Date Feb. 23, 1994 PCT Filed Aug. 10, 1992 PCT Pub. No. WO93/04501 PCT Pub. Date Mar. 4, 1993A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.

公开(公告)号：EP0551306A1

公开(公告)日：1993-07-21

申请号：EP91916654.0

申请日：1991-09-25

申请人： MITEL CORPORATION

发明人： OUELLET, Luc

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L21/02337 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76828 ,  Y10S438/974

摘要： Procédé de fabrication d'une tranche de semi-conducteur, comprenant: le dépôt d'une première couche de matériau d'interconnexion sur un substrat; l'attaque du matériau d'interconnexion pour former des circuits d'interconnexion; la réalisation d'une première métallisation pour déposer une première couche diélectrique à basse température au-dessus des circuits d'interconnexion; l'aplanissement de la première couche diélectrique à basse température au moyen de verre filé quasi-inorganique ou inorganique par un procédé contraire à la gravure en retrait; le dépôt d'une deuxième couche diélectrique à basse température au-dessus du verre filé, la réalisation d'une désorption in-situ physique et chimique de vapeur d'eau dans une ambiance sèche à une température d'au moins 400 °C et non supérieure à 550 °C pendant une durée suffisante pour obtenir un taux de désorption négligeable, la température dépassant d'au moins 25 °C la température à laquelle la surface de la tranche sera exposée pendant une étape de métallisation ultérieure; la gravure de trous de transit à travers les couches de verre filé et diélectrique pour atteindre les circuits de la première couche d'interconnexion et la réalisation de l'étape de métallisation ultérieure pour déposer une deuxième couche d'interconnexion passant par les trous de transit vers les premiers circuits d'interconnexion tout en maintenant l'ambiance sèche. Les étapes ultérieures de gravure et de métallisation suivant l'étape de désorption sont effectuées sans re-exposer la tranche aux conditions ambiantes. Cette technique permet d'utiliser avec fiabilité des verres filés inorganiques et quasi-inorganiques dans un équipement de pulvérisation sans charge.

公开(公告)号：EP1109349A2

公开(公告)日：2001-06-20

申请号：EP00311217.4

申请日：2000-12-15

申请人： Mitel Corporation

发明人： Spijker, Menno ,  Jeffery, George

IPC分类号： H04L7/00 ,  H04L12/56 ,  H04J3/06

CPC分类号： H04J3/0697 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0994 ,  H04J3/0632 ,  H04J3/0685 ,  H04L7/033 ,  H04L2012/5616 ,  H04L2012/5627 ,  H04L2012/5654 ,  H04L2012/5674 ,  H04Q11/0478

摘要： The invention relates to packet switched networks, and more particularly to a circuit and a method for clock recovery in cell-relay networks, particularly ATM (Asynchronous Transfer Mode) networks offering constant bit rate services. The multimode clock recovery circuit has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

摘要翻译： 本发明涉及分组交换网络，更具体地说，涉及一种在小区中继网络中，特别是提供恒定比特率服务的ATM（异步传输模式）网络中的时钟恢复的电路和方法。 多模时钟恢复电路具有嵌入式数字锁相环，其包括能够从至少两种类型的输入信号产生相位信号的输入电路。 控制锁相环输出的相位信号产生恒定比特率服务的时钟信号。

公开(公告)号：EP0855737A2

公开(公告)日：1998-07-29

申请号：EP97310627.1

申请日：1997-12-24

申请人： MITEL CORPORATION

发明人： Ouellet, Luc ,  Azelmad, Abdallah

IPC分类号： H01L21/033 ,  H01L21/31

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  Y10S438/942

摘要： A method of fabricating a semiconductor device includes etching hcles through at least one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned with the aid of a photoresist and holes are etched in the hard mask. After removal of the photoresist, contact or via holes are etched through the patterned hard mask in the deposited layer(s) to reach the underlying structure.

摘要翻译： 制造半导体器件的方法包括通过至少一个沉积层蚀刻至下面的结构。 将硬掩模沉积在要被蚀刻的器件的上表面上，借助光刻胶对掩模进行图案化，并且在硬掩模中蚀刻出空穴。 去除光刻胶之后，通过沉积层中的图案化硬掩模蚀刻接触孔或通孔以到达下面的结构。

公开(公告)号：EP0707766B1

公开(公告)日：1997-06-04

申请号：EP94920350.9

申请日：1994-07-04

申请人： MITEL CORPORATION

发明人： CHING, Philip, B., F.

IPC分类号： H04L25/40

CPC分类号： H04L25/40

摘要： A method is disclosed for extracting data words from a binary serial bit stream having a fixed bit rate and consisting of fixed length words of n bits each, where n is an integer, each word is preceded by a start bit and followed by one or more stop bits. First a predetermined identifiable transition is detected in said bit stream preceding each data word. A clock signal (DCLK) consisting of n clock pulses is generated in response to each detection of the predetermined transition in coincidence with the bits of the data word following the predetermined transition. A data ready signal (DR) is generated after the passage of n bits to delineate the word boundary, and the data words are extracted from the bit stream using the thus generated clock pulses and the data ready signal.