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    Method, an alignment mark and use of a hard mask material
    5.
    发明公开
    Method, an alignment mark and use of a hard mask material 审中-公开
    Verfahren，Ausrichtungsmarkierung und Nutzung eines harten Maskenmaterials

    公开(公告)号：EP1912257A2

    公开(公告)日：2008-04-16

    申请号：EP07118020.2

    申请日：2007-10-08

    申请人： ASML Netherlands BV

    发明人： van Haren, Richard Johannes Franciscus ,  Mos, Everhardus Cornelis

    IPC分类号： H01L23/544 ,  G03F9/00

    CPC分类号： G03F9/7084 ,  G03F9/708 ,  H01L21/3212 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： In a method to produce an alignment mark, an oxide layer (1010) and sacrificial layer are processed to comprise recesses. The recesses are filled with a filler material. During filling the recesses a layer of filler material is formed on the sacrificial layer. The layer of filler material is removed by chemical mechanical polishing. The sacrificial layer protects the oxide layer during filling the recesses and removing the layer of filler material. The sacrificial layer is then removed by etching. This provides an unscratched oxide layer with protrusions (1230). The oxide layer with protrusions is covered with a conducting layer (1070) whereby the protrusions punch through the oxide layer to form related protrusions. The related protrusions form an alignment mark.

    摘要翻译： 在产生对准标记的方法中，氧化物层（1010）和牺牲层被加工成包括凹陷。 凹部填充有填充材料。 在填充凹槽期间，在牺牲层上形成一层填充材料。 通过化学机械抛光除去填充材料层。 牺牲层在填充凹部期间保护氧化物层并去除填充材料层。 然后通过蚀刻去除牺牲层。 这提供了具有突起（1230）的未切割氧化物层。 具有突起的氧化物层被导电层（1070）覆盖，由此突起穿过氧化物层以形成相关的突起。 相关突起形成对准标记。

    COMPLEMENTARY DIVISION MASK HAVING ALIGNMENT MARK, METHOD FOR FORMING ALIGNMENT MARK OF THE COMPLEMENTARY DIVISION MASK, SEMICONDUCTOR DEVICE MANUFACTURED BY USING THE COMPLEMENTARY DIVISION MASK, AND ITS MANUFACTURING METHOD
    7.
    发明公开
    COMPLEMENTARY DIVISION MASK HAVING ALIGNMENT MARK, METHOD FOR FORMING ALIGNMENT MARK OF THE COMPLEMENTARY DIVISION MASK, SEMICONDUCTOR DEVICE MANUFACTURED BY USING THE COMPLEMENTARY DIVISION MASK, AND ITS MANUFACTURING METHOD 审中-公开
    互补细分掩模对准MARK，方法形成取向互补细分MASK标记使用由半导体部件及其制造方法互补细分MASK

    公开(公告)号：EP1548805A1

    公开(公告)日：2005-06-29

    申请号：EP03766745.8

    申请日：2003-08-05

    申请人： Sony Corporation

    发明人： NOHDO, Shinichiro, c/o SONY CORPORATION ,  AMAI, Keiko, c/o SONY CORPORATION

    IPC分类号： H01L21/027 ,  G03F1/16 ,  G03F7/20

    CPC分类号： G03F1/20 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01J2237/30438

    摘要： In fabrication of a semiconductor device having plural patterns on a plurality of layers by using complementary divided masks each having alignment marks distributed therein, because of the presence of a plurality of complementary divided mask layers, misalignment between respective layers tends to occur. To solve this problem, divided alignment marks (M1a, M2a, M3a, M4a) are formed in respective complementary divided regions corresponding to respective blocks (B1, B2, B3, B4) of complementary divided masks obtained by dividing a stencil mask. By distributing alignment marks to respective complementary divided masks, a positional deviation between respective masks is averaged, thereby enabling to fabricate a semiconductor device in which a large positional deviation between patterns of adjoining layers is eliminated.

    摘要翻译： 在具有通过使用互补的分割的掩膜上层上的多个复数图案的半导体器件的制造。其中分布式因为互补分割掩模层上的多个的存在的每一个具有对准标记，层respectivement之间的未对准趋于发生。 为了解决这个麻烦，分对准标记（M1a的，M2A，M3A，M4A）形成在respectivement互补分割区域对应于respectivement通过将模版掩模获得互补分割的掩膜的块（B1，B2，B3，B4）。通过分配 对准标记respectivement互补分割的掩膜，respectivement掩模之间的位置偏差进行平均，从而能够制造在其中相邻层的图案之间的大的位置偏差被消除的半导体器件。

    DESIGN OF LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS ON DAMASCENE SURFACE
    8.
    发明公开
    DESIGN OF LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS ON DAMASCENE SURFACE 有权
    品牌平版准则和COVER测上DAMASZENOBERFLÄCHE设计

    公开(公告)号：EP1354358A2

    公开(公告)日：2003-10-22

    申请号：EP02723082.0

    申请日：2002-01-24

    申请人： Infineon Technologies AG

    发明人： NING, Xian, J.

    IPC分类号： H01L23/544

    CPC分类号： G03F9/708 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/822 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for producing a semiconductor device having an alignment mark, the method comprising forming a first dielectric layer within which a trench having predetermined dimensions is etched and depositing a first layer of metal into the trench; forming a second dielectric layer over the first dielectric layer and over the first layer of metal; simultaneously etching lines and an opening into the second dielectric layer, at least one line used as a via extending to the first layer of metal; filling the lines and the opening, the filling controlled to fill the lines and to under fill the opening; performing chemical mechanical polishing of the plate; and depositing a non-transparent stack of layers onto the metal, whereby the non-transparent stack of layers conforms to the surface of the under filled opening resulting in an alignment mark on the non-transparent stack of layers in order to align successive layers.

    MARK STRUCTURE AND FABRICATION METHOD THEREOF
    9.
    发明公开
    MARK STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
    标记结构及其制造方法

    公开(公告)号：EP3203322A1

    公开(公告)日：2017-08-09

    申请号：EP17152668.4

    申请日：2017-01-23

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： LU, Daoliang ,  ZHANG, Hongwei ,  FENG, Kui

    IPC分类号： G03F7/20 ,  G03F9/00

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L2223/5446

    摘要： The present invention provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

    摘要翻译： 本发明提供了其标记结构和制造方法。 示例性制造工艺包括提供具有器件区域，第一标记区域和第二标记区域的衬底; 在衬底的表面上依次形成器件层，电介质层和掩模层; 在器件区域中的电介质层中形成第一开口，第一标记区域中的电介质层中的第一标记和第二标记区域中的电介质层中的标记开口，第一开口的底部，第一标记和 标记开口低于介电层的表面并且高于器件层的表面; 以及在第一开口的底部上的介电层中形成第二开口，并且在标记开口的底部上的介电层中形成第二标记。

    IMPRINT APPARATUS, MOLD, IMPRINT METHOD, AND METHOD OF MANUFACTURING ARTICLE
    10.
    发明公开
    IMPRINT APPARATUS, MOLD, IMPRINT METHOD, AND METHOD OF MANUFACTURING ARTICLE 审中-公开
    实施例，形式，实施例和制造文章的方法

    公开(公告)号：EP2826060A4

    公开(公告)日：2015-08-05

    申请号：EP13761347

    申请日：2013-02-13

    申请人： CANON KK

    发明人： SHIODE YOSHIHIRO

    IPC分类号： H01L21/027 ,  B29C59/02 ,  G03F7/00

    CPC分类号： B29C59/002 ,  B29C59/022 ,  B29C2059/023 ,  G03F7/0002 ,  G03F9/7073 ,  G03F9/708 ,  G03F9/7084 ,  G03F9/7088

    摘要： The present invention provides an imprint apparatus which transfers a pattern onto a substrate by using a mold including a first surface with a pattern region where an unevenness pattern is formed, and a second surface opposite to the first surface, the mold including a first pattern group formed between the second surface and a surface of a convex portion in the unevenness pattern, or on the second surface, the apparatus comprising a second pattern group, a detection unit configured to detect a mark group formed by light having passed through the first pattern group and the second pattern group, and a calculation unit configured to calculate a position deviation between the first pattern group and the second pattern group from the mark group detected by the detection unit.