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    SEMICONDUCTOR DEVICE WITH PROTECTED SIDEWALLS
    1.
    发明公开
    SEMICONDUCTOR DEVICE WITH PROTECTED SIDEWALLS 审中-公开
    具有受保护侧壁的半导体器件

    公开(公告)号：EP3258488A1

    公开(公告)日：2017-12-20

    申请号：EP17165113.6

    申请日：2017-04-05

    申请人： Nexperia B.V.

    发明人： Funke, Hans-Juergen ,  Sprogies, Tobias ,  Brenner, Rolf ,  Weber, Rüdiger ,  Schnitt, Wolfgang ,  Burmeister, Frank

    IPC分类号： H01L23/31 ,  H01L21/784 ,  H01L21/56 ,  H01L21/82

    CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L21/784 ,  H01L21/82 ,  H01L23/3121 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2924/3841

    摘要： A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.

    摘要翻译： 公开了一种保护侧壁多个半导体器件的方法。 该方法包括在半导体晶片上制造多个半导体器件，蚀刻以在半导体晶片的背面上形成沟槽栅格网络。 沟槽网格网络划分多个半导体器件中每一个的物理边界。 该方法还包括在背面上沉积保护层并且蚀刻以从水平表面去除保护层并且从半导体晶片切割出多个半导体器件中的每一个。

    MARK STRUCTURE AND FABRICATION METHOD THEREOF
    3.
    发明公开
    MARK STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
    标记结构及其制造方法

    公开(公告)号：EP3203322A1

    公开(公告)日：2017-08-09

    申请号：EP17152668.4

    申请日：2017-01-23

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： LU, Daoliang ,  ZHANG, Hongwei ,  FENG, Kui

    IPC分类号： G03F7/20 ,  G03F9/00

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L2223/5446

    摘要： The present invention provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

    摘要翻译： 本发明提供了其标记结构和制造方法。 示例性制造工艺包括提供具有器件区域，第一标记区域和第二标记区域的衬底; 在衬底的表面上依次形成器件层，电介质层和掩模层; 在器件区域中的电介质层中形成第一开口，第一标记区域中的电介质层中的第一标记和第二标记区域中的电介质层中的标记开口，第一开口的底部，第一标记和 标记开口低于介电层的表面并且高于器件层的表面; 以及在第一开口的底部上的介电层中形成第二开口，并且在标记开口的底部上的介电层中形成第二标记。

    BONDING PAD ARRANGEMENT DESIGN FOR SEMICONDUCTOR PACKAGE
    4.
    发明公开
    BONDING PAD ARRANGEMENT DESIGN FOR SEMICONDUCTOR PACKAGE 审中-公开
    BONDPAD-ANORDNUNGSENTWURFFÜRHALBLEITERGEHÄUSE

    公开(公告)号：EP3091569A1

    公开(公告)日：2016-11-09

    申请号：EP16156420.8

    申请日：2016-02-19

    申请人： MediaTek, Inc

    发明人： CHEN, Ying-Chih ,  CHOU, Che-Ya ,  LIN, Min-Yu ,  YANG, Chia-Hao ,  CHU, Wen-Pin

    IPC分类号： H01L23/482 ,  H01L23/49 ,  H01L25/065

    CPC分类号： H01L25/0657 ,  H01L23/3171 ,  H01L23/4821 ,  H01L23/544 ,  H01L24/06 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/5446 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/4813 ,  H01L2224/49052 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

    摘要： A semiconductor memory package is provided. The package includes a semiconductor die having a first die portion (100a) and a second die portion (100c). A -passivation layer (102) is on the semiconductor die (100). A first post-passivation interconnect (PPI) structure includes pluralities of first and second pads (104,106) arranged in first and second tiers (201, 202), respectively. The first and second pads (104, 106) are disposed on a first die (100a) portion of the semiconductor die (100). A second PPI structure includes pluralities of third and fourth pads (108,110) arranged in third and fourth tiers (203, 204), respectively. The third and fourth pads (108,110) are disposed on a second die portion (100b) of the semiconductor die (100). One of the first pads (104) and one of the fourth pads (110) are coupled to each other by a first bonding wire (120). One of the second pads (106) and one of the third pads (110) are coupled to each other by a second bond wire (130).

    摘要翻译： 提供半导体存储器封装。 该封装包括具有第一裸片部分（100a）和第二裸片部分（100c）的半导体管芯。 A钝化层（102）位于半导体管芯（100）上。 第一后钝化互连（PPI）结构包括分别布置在第一和第二层（201,202）中的多个第一和第二焊盘（104,106）。 第一和第二焊盘（104,106）设置在半导体管芯（100）的第一管芯（100a）部分上。 第二PPI结构包括分别布置在第三层和第四层（203,204）中的多个第三和第四衬垫（108,110）。 第三和第四焊盘（108,110）设置在半导体管芯（100）的第二管芯部分（100b）上。 第一焊盘（104）和第四焊盘（110）中的一个通过第一接合线（120）彼此耦合。 第二焊盘（106）中的一个和第三焊盘（110）中的一个通过第二接合线（130）彼此耦合。

    THERMAL STRESS REDUCTION
    8.
    发明公开
    THERMAL STRESS REDUCTION 审中-公开
    热应力折减

    公开(公告)号：EP2220673A1

    公开(公告)日：2010-08-25

    申请号：EP08848778.0

    申请日：2008-11-07

    申请人： NXP B.V.

    发明人： COUSIN, Alain

    IPC分类号： H01L21/304 ,  H01L23/544

    CPC分类号： H01L23/544 ,  H01L21/02005 ,  H01L21/78 ,  H01L28/90 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 μm, preferably from 5-40 μm, like 20 μm.