中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.013 seconds)

    SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED CIRCUITS
    2.
    发明公开
    SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED CIRCUITS 审中-公开
    系统和方法用于测试的可靠性保证集成电路

    公开(公告)号：EP2737490A1

    公开(公告)日：2014-06-04

    申请号：EP12751641.7

    申请日：2012-07-27

    Applicant: Tessera, Inc.

    Inventor： PARRIS, Michael, Curtis

    IPC: G11C29/02

    CPC classification number: G01R31/07 ,  G11C29/027

    Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre- charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.

    DUAL FUNCTION DATA REGISTER
    5.
    发明公开
    DUAL FUNCTION DATA REGISTER 有权
    二元函数的数据寄存器

    公开(公告)号：EP2122632A1

    公开(公告)日：2009-11-25

    申请号：EP07855567.9

    申请日：2007-12-20

    Applicant: Sidense Corp.

    Inventor： KURJANOWICZ, Wlodek

    IPC: G11C19/00 ,  G11C17/14 ,  G11C7/22 ,  H03K5/13

    CPC classification number: G11C29/52 ,  G11C5/143 ,  G11C16/3454 ,  G11C16/3459 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C19/00 ,  G11C29/027 ,  G11C2029/0407

    Abstract: A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.

    PROGRAMMABLE MEMORY REPAIR SCHEME
    9.
    发明公开
    PROGRAMMABLE MEMORY REPAIR SCHEME 审中-公开
    REPARATURSCHEMAFÜRPROGRAMMIBAREN SPEICHER

    公开(公告)号：EP2301038A1

    公开(公告)日：2011-03-30

    申请号：EP09730954.6

    申请日：2009-04-09

    Applicant: Rambus Inc.

    Inventor： ONG, Adrian, E. ,  HO, Fan

    IPC: G11C29/00

    CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

    Abstract: The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

    Abstract translation: 本公开提供了用于测试和操作该半导体器件的方法，系统和装置。 半导体存储器件包括数据存储元件和修复电路。 数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器访问操作的相应地址。 修复电路可以由与存储器件分离的另一个半导体器件编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将具有识别的故障地址的主数据存储元件的存储器访问重新路由到相应的 冗余数据存储元件。

    METHOD OF PROVIDING OPTIMAL FIELD PROGRAMMING OF ELECTRONIC FUSES
    10.
    发明授权
    METHOD OF PROVIDING OPTIMAL FIELD PROGRAMMING OF ELECTRONIC FUSES 有权
    方法提供电子熔化连接操作的大部分编程

    公开(公告)号：EP2078304B1

    公开(公告)日：2011-03-23

    申请号：EP07821474.9

    申请日：2007-10-17

    Applicant: International Business Machines Corporation

    Inventor： OUELLETTE, Michael, Richard ,  PERRY, Troy, Joseph

    IPC: G11C17/00

    CPC classification number: G11C17/18 ,  G11C17/165 ,  G11C29/027

    Abstract: A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.

Patent Agency Ranking