公开(公告)号：EP3167452A4

公开(公告)日：2018-03-07

申请号：EP14897113

申请日：2014-07-08

申请人： INTEL CORP

发明人： BOU-GHAZALE SILVIO E ,  GHOSH ABHIK ,  GOEL NITI

IPC分类号： G11C29/00 ,  G06F11/20 ,  G06F17/50 ,  G11C5/02

CPC分类号： G03F7/705 ,  G06F11/2041 ,  G06F17/5068 ,  G06F17/5081 ,  G11C5/025 ,  G11C29/702 ,  G11C29/814 ,  G11C29/816 ,  G11C29/88

摘要： Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.

公开(公告)号：EP3161854A4

公开(公告)日：2018-05-30

申请号：EP14896073

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ASKSAMIT RANDY J

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

公开(公告)号：EP3161840A4

公开(公告)日：2018-05-23

申请号：EP14895620

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ROY ANSHUMALI ,  YIP JOSEPH C

IPC分类号： H01F17/00 ,  G03F7/20 ,  H01F41/04 ,  H01G4/012 ,  H01G4/32 ,  H01G4/40 ,  H01L49/02

CPC分类号： H01L23/66 ,  G03F7/2059 ,  H01F17/0006 ,  H01F41/042 ,  H01G4/012 ,  H01G4/40 ,  H01L28/10 ,  H01L28/60 ,  H01L2223/6672

摘要： Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.