公开(公告)号：EP3161854A4

公开(公告)日：2018-05-30

申请号：EP14896073

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ASKSAMIT RANDY J

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

公开(公告)号：EP3161840A4

公开(公告)日：2018-05-23

申请号：EP14895620

申请日：2014-06-25

申请人： INTEL CORP

发明人： ELSAYED RANY T ,  GOEL NITI ,  BOU-GHAZALE SILVIO E ,  ROY ANSHUMALI ,  YIP JOSEPH C

IPC分类号： H01F17/00 ,  G03F7/20 ,  H01F41/04 ,  H01G4/012 ,  H01G4/32 ,  H01G4/40 ,  H01L49/02

CPC分类号： H01L23/66 ,  G03F7/2059 ,  H01F17/0006 ,  H01F41/042 ,  H01G4/012 ,  H01G4/40 ,  H01L28/10 ,  H01L28/60 ,  H01L2223/6672

摘要： Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.

公开(公告)号：EP3161866A4

公开(公告)日：2018-03-14

申请号：EP14895959

申请日：2014-06-27

申请人： INTEL CORP

发明人： BOU GHAZALE SILVIO E ,  ELSAYED RANY T ,  GOEL NITI

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L27/0629 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.