公开(公告)号：EP2979308A1

公开(公告)日：2016-02-03

申请号：EP14715249.0

申请日：2014-03-28

申请人： Aledia

发明人： SCARINGELLA, Sylvia ,  GILET, Philippe ,  HUGON, Xavier ,  GIBERT, Philippe

IPC分类号： H01L33/08 ,  H01L33/18 ,  H01L33/38 ,  B82Y20/00 ,  H01L33/24

CPC分类号： H01L33/06 ,  B82Y20/00 ,  H01L24/03 ,  H01L24/05 ,  H01L33/08 ,  H01L33/18 ,  H01L33/24 ,  H01L33/32 ,  H01L33/38 ,  H01L33/42 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05078 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2933/0016 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00014

摘要： The invention relates to an electroluminescent device comprising an array of nanowires (Nti) over the entirety of the surface of a substrate (100), characterised in that: it comprises at least one first series of first nanowires and one second series of second nanowires; said first series comprises first nanowires, called active nanowires (NTi
a ), that are capable of emitting light under electrical control, said nanowires being connected between a first type of electrical contact and a second type of electrical contact in order to allow said device to emit light under electrical control, said first nanowires being covered with at least one conductive layer (300) that is transparent at the emission wavelength of said electroluminescent device, said layer making contact with said first type of electrical contact; said second series comprises second nanowires, called contact nanowires (NTi
c ), that are encapsulated in a metal layer (700) allowing said first type of electrical contact to be formed; and the second type of electrical contact is located on the backside of said substrate, opposite the side comprising said nanowires, and is formed by a conductive layer at least facing said first series of nanowires. The invention also relates to a method for producing said electroluminescent device.

公开(公告)号：EP3341956A1

公开(公告)日：2018-07-04

申请号：EP16840097.6

申请日：2016-08-25

申请人： Invensas Bonding Technologies, Inc.

发明人： ENQUIST, Paul, M.

IPC分类号： H01L21/18 ,  H01L21/52 ,  H01L23/00

CPC分类号： H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/05005 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/8019 ,  H01L2224/80895 ,  H01L2225/06513

摘要： A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：EP3217427A1

公开(公告)日：2017-09-13

申请号：EP16199543.6

申请日：2016-11-18

申请人： MediaTek Inc.

发明人： JI, Yan-Liang ,  HSIUNG, Ming-Jen

IPC分类号： H01L23/485

CPC分类号： H01L23/3171 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/94 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/94

摘要： A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

摘要翻译： 晶圆级芯片尺寸封装包括半导体结构。 焊盘形成在半导体结构上方，包括多个导电段。 导电组件形成在半导体结构上方，与键合焊盘相邻。 形成钝化层，暴露第一键合焊盘的部分导电段。 导电再分布层形成在由钝化层暴露的第一键合焊盘的导电段的部分上方。 平坦化层形成在钝化层和导电再分布层上，暴露导电再分布层的一部分。 UBM层形成在平坦化层和由平坦化层暴露的部分导电再分布层上。 在UBM层上形成导电凸块。

公开(公告)号：EP3147259A1

公开(公告)日：2017-03-29

申请号：EP16190392.7

申请日：2016-09-23

申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

发明人： CHEN, Fu Cheng ,  SHI, Lin Bo ,  LIU, Yao

IPC分类号： B81C1/00

CPC分类号： H01L24/05 ,  B81B2207/093 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  H01L24/02 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/05013 ,  H01L2224/05078 ,  H01L2224/052 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/1461 ,  H01L2924/3841

摘要： The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal block made of a second metal material. The plurality of first metal blocks are configured to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.

摘要翻译： 本公开提供接合垫结构，结合环结构; 和MEMS器件封装方法。 示例性的焊盘结构包括由第一金属材料制成的多个第一金属块; 以及由第二金属材料制成的多个第二金属块。 多个第一金属块被构造成防止多个第二金属块的挤出和延伸。 在焊盘结构的至少一个等分平面上，第一金属材料至少示出一次; 并且第二金属材料至少显示一次。