公开(公告)号：EP3341956A1

公开(公告)日：2018-07-04

申请号：EP16840097.6

申请日：2016-08-25

申请人： Invensas Bonding Technologies, Inc.

发明人： ENQUIST, Paul, M.

IPC分类号： H01L21/18 ,  H01L21/52 ,  H01L23/00

CPC分类号： H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/05005 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/8019 ,  H01L2224/80895 ,  H01L2225/06513

摘要： A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：EP3118892B1

公开(公告)日：2018-05-02

申请号：EP14885109.0

申请日：2014-12-26

申请人： Thruchip Japan Inc.

发明人： KURODA, Tadahiro

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

公开(公告)号：EP3285294A1

公开(公告)日：2018-02-21

申请号：EP17185777.4

申请日：2017-08-10

申请人： EM Microelectronic-Marin SA

发明人： Kuratli, Christoph ,  Dupraz, Yves

IPC分类号： H01L23/485 ,  H01L23/544 ,  H01L23/528

CPC分类号： H01L24/09 ,  G01R31/31715 ,  G01R31/31937 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06167 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/014

摘要： The invention relates to an electronic system comprising:
- an integrated circuit die (10') having:
• at least 2 bond pads (20, 37)
• a redistribution layer, said redistribution layer having:
- at least a solder pad (19') comprising 2 portions (33, 34) arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad (19'), but electrically isolated of each other in the absence of a solder ball on the solder pad (19')
- at least 2 redistribution wires (22, 23, 39), each one connecting one of the 2 portions (33, 34) to one of the 2 bond pads (20, 37),

a second bond pad (37) connected via a second redistribution wire (39) to a second portion (34) of the solder pad (19') being dedicated to testing said integrated circuit die (10')
- a grounded printed circuit board track (24), a solder ball (35) being placed between the solder pad (19') and the printed circuit board track (24).

摘要翻译： 本发明涉及一种电子系统，包括： - 集成电路管芯（10'），其具有：·至少2个接合焊盘（20,37）·重新分布层，所述重新分布层具有： - 至少一个焊盘（19' ）包括布置成通过放置在所述焊盘（19'）上的相同焊球实现彼此之间的电连接的两个部分（33,34），但是在焊盘上没有焊球的情况下彼此电隔离 （19）; - 至少两个再分配线（22,23,39），每个再分配线将两个部分（33,34）中的一个连接到2个键合焊盘（20,37）中的一个，第二键合焊盘（37 ）经由第二再分布线（39）连接到专用于测试所述集成电路管芯（10'）的焊盘（19'）的第二部分（34） - 接地印刷电路板轨道（24），焊料 球（35）放置在焊料垫（19'）和印刷电路板轨道（24）之间。

公开(公告)号：EP3118892A1

公开(公告)日：2017-01-18

申请号：EP14885109.0

申请日：2014-12-26

申请人： Thruchip Japan Inc.

发明人： KURODA, Tadahiro

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

摘要翻译： 本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。 第一半导体集成电路器件设置有第一贯穿半导体区域和第二贯穿半导体区域，第一贯穿半导体区域在厚度方向上贯穿第一半导体本体并且连接到第一电源电位，第二贯穿半导体区域贯穿第一半导体本体 厚度方向并且连接到第二电源电位。 具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。

公开(公告)号：EP3066683A1

公开(公告)日：2016-09-14

申请号：EP13896994.4

申请日：2013-11-07

申请人： Freescale Semiconductor, Inc.

发明人： VOLOKHINE, Youri

IPC分类号： H01L21/60

CPC分类号： H03K17/689 ,  H01L23/66 ,  H01L24/05 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/09505 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/49052 ,  H01L2224/49096 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F3/193 ,  H03F3/213 ,  H03F2200/411 ,  H03F2200/451 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

摘要： The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

摘要翻译： 本发明提供了一种接合线布置，其包括用于将第一电子设备（6）可操作地连接到第二电子设备（8）的信号接合线（1），以及控制接合线（2），其沿信号接合线 一个距离，以便与信号接合线（1）具有磁耦合，并且具有耦合到地的第一端（11）和经由电阻元件（14）耦合到地的第二端（12）。 所提出的解决方案允许在组装阶段控制焊线电感器的Q因子（损耗），与已知方法相比，这将节省时间并减少整体设计周期。

公开(公告)号：EP2973672A1

公开(公告)日：2016-01-20

申请号：EP14722830.8

申请日：2014-03-12

申请人： Materion Corporation

发明人： KOTHANDAPANI, Ramesh

IPC分类号： H01L21/60 ,  H01L23/488

CPC分类号： H01L24/09 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2711 ,  H01L2224/27334 ,  H01L2224/2746 ,  H01L2224/29144 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/1033 ,  H01L2924/0105 ,  H01L2924/01032 ,  H01L2924/01074 ,  H01L2924/00015

摘要： The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations.

摘要翻译： 金用于粘合半导体的电子封装件所需要的量是通过使用焊接到封装安装在模头之前的片材预制件的粘性降低。 的预制件，仅略微比要被连接到封装的半导体时，在在两个隔开的位置焊接到包装中的粘结位置和粘性放置。

公开(公告)号：EP2916459A1

公开(公告)日：2015-09-09

申请号：EP14164931.9

申请日：2014-04-16

申请人： MediaTek, Inc

发明人： Liu, Der-Ping ,  Lu, Tai-You

IPC分类号： H03L7/06 ,  G06F1/10 ,  H01L25/065 ,  H01L23/552

CPC分类号： H01L23/49838 ,  G06F1/10 ,  H01L23/528 ,  H01L23/552 ,  H01L24/09 ,  H01L24/17 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip is provided. The semiconductor chip includes a first circuit, a second circuit, a third circuit, a first signal path and a second signal path. The first circuit provides a reference signal. The first signal path includes a first conductive trace and transmits the reference signal from the first circuit to the second circuit. The second signal path transmits the reference signal from the first circuit to the third circuit. Timing skews of the first and second signal paths are balanced and the first and second signal paths are routed globally.

摘要翻译： 提供半导体芯片。 半导体芯片包括第一电路，第二电路，第三电路，第一信号路径和第二信号路径。 第一个电路提供参考信号。 第一信号路径包括第一导电迹线并将参考信号从第一电路传输到第二电路。 第二信号路径将参考信号从第一电路传输到第三电路。 平衡第一和第二信号路径的时序偏移，并且第一和第二信号路径被全局路由。

公开(公告)号：EP2916351A2

公开(公告)日：2015-09-09

申请号：EP15152958.3

申请日：2015-01-28

申请人： Intel Corporation

发明人： Meyer, Thorsten ,  Albers, Sven

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L24/09 ,  G06F1/1613 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/0903 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1047 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/00012

摘要： Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了集成电路（IC）封装组件和制造IC封装组件的方法。 这些实施例包括嵌入在衬底中以提供较大间距互连以便于通过倒装芯片技术耦合到衬底或电路板的裸片。 嵌入衬底可以包含用于将裸片触点耦合到位于嵌入衬底上的较大间距触点的导电路径。 通过将模具嵌入到嵌入基板中，具有较小节距触点的模具可用于具有较大间距部件的封装组件中，而不需要硅插入件，并且不必采用更严格的拾取和放置操作。 可以描述和/或要求保护其他实施例。

公开(公告)号：EP2876679A2

公开(公告)日：2015-05-27

申请号：EP14187829.8

申请日：2014-10-06

申请人： Renesas Electronics Corporation

发明人： Ishii, Yasushi ,  Adachi, Tetsuo

IPC分类号： H01L23/485 ,  H01L21/66 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L23/3107 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03831 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/09051 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20753

摘要： This invention provides a semiconductor device with improved reliability. The semiconductor device (CHP1) comprising:a semiconductor substrate (SS) having an element formation surface;a first insulating film (PVL) that has a first surface (PVb) facing the semiconductor substrate (SS), a second surface (PVt) opposite to the first surface (PVb), and a plurality of openings (PVk) passing therethrough from one of the first surface (PVb) and the second surface (PVt) to the other in the thickness direction, and is formed so as to cover the element formation surface of the semiconductor substrate (SS); anda plurality of electrode pads (PD1, PD2, PD3) that are formed between the first insulating film (PVL) and the semiconductor substrate (SS), and are exposed from the first insulating film (PVL) at positions overlapping the openings (PVk) in the first insulating film (PVL),wherein, the electrode pads include:a plurality of the first-line electrode pads (PD1) formed in a first line along a first chip side (Cs1) of a perimeter of the second surface in plan view;a plurality of second-line electrode pads (PD2) formed in a second line along the first chip side (Cs1), the second line located further than the first line from the first chip side (Cs1) in plan view; anda plurality of third-line electrode pads (PD3) formed in a third line along the first chip side (Cs1), the third line located further than the second line from the first chip side (Cs1) in plan view, and wherein, the areas of the respective first-line electrode pads (PD1) are smaller than the areas of the respective second-line electrode pads (PD2) and the respective third-line electrode pads (PD3).

公开(公告)号：EP2538436B1

公开(公告)日：2015-03-25

申请号：EP12161184.2

申请日：2012-03-26

申请人： Raytheon Company

发明人： Moody, Cody

IPC分类号： H01L21/50 ,  H01L21/56 ,  H01L23/10 ,  H01L21/60 ,  H01L23/00 ,  B81C1/00

CPC分类号： H01L24/83 ,  H01L21/563 ,  H01L23/10 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/26135 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29686 ,  H01L2224/32055 ,  H01L2224/32148 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00