公开(公告)号：EP3176819A2

公开(公告)日：2017-06-07

申请号：EP16199908.1

申请日：2016-11-22

申请人： MediaTek Inc.

发明人： JI, Yan-Liang ,  HSIUNG, Ming-Jen

IPC分类号： H01L23/31

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

摘要翻译： 晶片级芯片级封装（WLCSP）包括半导体结构和形成在半导体结构的一部分上的第一焊盘。 WLCSP还包括形成在半导体结构上的钝化层和第一焊盘，暴露第一焊盘的部分。 WLCSP还包括形成在钝化层上的导电再分布层和由钝化层暴露的第一焊盘的部分。 WLCSP还包括形成在钝化层和导电再分配层上的平坦化层，暴露导电再分布层的一部分。 WLCSP还包括在平坦化层上形成的凸点下 - 冶金（UBM）层和形成在UBM层上的导电凸块。

公开(公告)号：EP1107307B1

公开(公告)日：2005-09-07

申请号：EP00935668.4

申请日：2000-06-13

申请人： FUJIKURA LTD. ,  TEXAS INSTRUMENTS JAPAN LTD.

发明人： SUZUKI, Takanao Fujikura Ltd. ,  INABA, Masatoshi Fujikura Ltd. ,  OMINATO, Tadanori Fujikura Ltd. ,  KAIZU, Masahiro Fujikura Ltd. ,  KUROSAKA, Akihito Fujikura Ltd. ,  INABA, Masatoshi Fujikura Ltd. ,  SADAKATA, Nobuyuki Fujikura Ltd. ,  MASUMOTO, Mutsumi Texas Instruments Japan Limited ,  MASUMOTO, Kenji Texas Instruments Japan Limited

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/485

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) is formed to have an opening (3a) corresponding to an electrode pad (2). A projection (4) of resin is then formed on the insulating layer (3). A resist layer is formed to have openings corresponding to the opening (3a), the projection (4) and the area between them. A Cu-plated layer (6) is formed by electrodeposition using the resist layer as a mask.

公开(公告)号：EP2338170A1

公开(公告)日：2011-06-29

申请号：EP09785641.3

申请日：2009-09-14

申请人： Cambridge Silicon Radio Limited

发明人： HOLLAND, Andrew

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60

CPC分类号： H01L24/94 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/12 ,  H01L24/17 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014

摘要： An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

公开(公告)号：EP2026380A2

公开(公告)日：2009-02-18

申请号：EP08162325.8

申请日：2008-08-13

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Kazama, Takuya

IPC分类号： H01L23/31 ,  H01L23/485

CPC分类号： H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02333 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14

摘要： There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate 21; (b) forming a plurality of semiconductor chips 11 having electrode pads 23 on the semiconductor substrate; (c) forming internal connection terminals 12 on the electrode pads; (d) forming an insulating layer 13 on the plurality of semiconductor chips to cover the internal connection terminals; (c) forming a metal layer 33 on the insulating layer; (f) pushing a whole area of the metal layer to bring the metal layer into contact with upper end portions 12-1 of the internal connection terminals; (g) pushing portions of the metal layer which contact the upper end portions of the internal connection terminals, thereby forming first recesses 12-1A in the internal connection terminals, and thereby forming second recesses 14A in the metal layer; and (h) forming wiring patterns 14 by etching the metal layer 33.

摘要翻译： 提供了一种制造半导体器件的方法。 该方法包括以下连续步骤：（a）提供半导体衬底21; （b）在半导体衬底上形成具有电极焊盘23的多个半导体芯片11; （c）在电极垫上形成内部连接端子12; （d）在多个半导体芯片上形成绝缘层13以覆盖内部连接端子; （c）在绝缘层上形成金属层33; （f）推动金属层的整个区域以使金属层与内部连接端子的上端部12-1接触; （g）推动与内部连接端子的上端部接触的金属层的部分，由此在内部连接端子中形成第一凹部12-1A，从而在金属层中形成第二凹部14A; 和（h）通过蚀刻金属层33来形成布线图案14。

公开(公告)号：EP1030357A4

公开(公告)日：2004-10-20

申请号：EP97909706

申请日：1997-10-30

申请人： HITACHI LTD

发明人： MIYAMOTO TOSHIO ,  ANJO ICHIRO ,  ARITA JUNICHI ,  EGUCHI SHUJI ,  KITANO MAKOTO ,  KUBO MASAHARU ,  MUNAKATA TAKESHI ,  FUKUDA TAKUYA

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L23/12

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： In a chip-size package, a low-elasticity elastomer (2) which relieves and absorbs the stresses concentrated upon bump electrodes (5) is formed on the main surface of a semiconductor chip (1), and the wiring (4) connected to bonding pads (7) is led out to the upper surface of the elastomer (2) by way of through holes formed through the elastomer (2) and connected to the bump electrodes (5). The stresses concentrated upon the bump electrodes (5) are absorbed and relieved by not only the elastomer (2), but also the expansion and contraction of the wiring (4) led out to the upper surface of the elastomer (2) by laying the wiring (4) in a curved pattern.

摘要翻译： 一种芯片尺寸封装，其中在半导体芯片的主面上形成用于阻尼和吸收应力的低弹性弹性体，否则可能集中在凸块电极上，并且其中与焊盘连接的导线被引出到 弹性体的上表面通过形成在弹性体中的通孔，并且在其一端部与凸起电极连接。 另一方面，引出到弹性体的上表面的电线被形成为弯曲图案，使得集中在凸块电极上的应力可以被不仅弹性体的伸缩而被吸收和阻尼 还有电线。

公开(公告)号：EP1107307A1

公开(公告)日：2001-06-13

申请号：EP00935668.4

申请日：2000-06-13

申请人： Fujikura Ltd. ,  TEXAS INSTRUMENTS JAPAN LTD.

发明人： SUZUKI, Takanao Fujikura Ltd. ,  INABA, Masatoshi Fujikura Ltd. ,  OMINATO, Tadanori Fujikura Ltd. ,  KAIZU, Masahiro Fujikura Ltd. ,  KUROSAKA, Akihito Fujikura Ltd. ,  INABA, Masatoshi Fujikura Ltd. ,  SADAKATA, Nobuyuki Fujikura Ltd. ,  MASUMOTO, Mutsumi Texas Instruments Japan Limited ,  MASUMOTO, Kenji Texas Instruments Japan Limited

IPC分类号： H01L21/60 ,  H01L23/12

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）一致的位置具有开口部（3a）的绝缘层（3）。 接下来，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，其具有在与开口部分（3a），树脂突出部分（4）和夹在其间的区域相适应的区域中形成的开口部分。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：EP1030357A1

公开(公告)日：2000-08-23

申请号：EP97909706.0

申请日：1997-10-30

申请人： Hitachi, Ltd.

发明人： MIYAMOTO, Toshio ,  ANJO, Ichiro ,  ARITA, Junichi ,  EGUCHI, Shuji ,  KITANO, Makoto ,  KUBO, Masaharu ,  MUNAKATA, Takeshi ,  FUKUDA, Takuya

IPC分类号： H01L21/60 ,  H01L23/12

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： A chip size package in which an elastomer of low elasticity for damping and absorbing a stress, as might otherwise be concentrated on bump electrodes, is formed over the principal face of a semiconductor chip and in which wires connected with bonding pads are led out to the upper face of the elastomer through through holes formed in the elastomer and are connected at their one-end portions with the bump electrodes. On the other hand, the wires, as led out to the upper face of the elastomer are formed in a curved pattern so that the stress to be concentrated on the bump electrodes may be absorbed and damped by the extension and contraction of not only the elastomer but also the wires.

摘要翻译： 一种芯片尺寸封装，其中在半导体芯片的主面上形成用于阻尼和吸收应力的低弹性弹性体（否则可能会集中在凸块电极上），并且其中将与焊盘相连的导线引出到 弹性体的上表面穿过形成在弹性体中的通孔并且在它们的一个端部与突起电极连接。 另一方面，引出到弹性体的上表面的导线以弯曲的方式形成，使得集中在凸块电极上的应力可以被吸收，并且不仅由于弹性体的伸缩而被阻尼 还包括电线。

公开(公告)号：EP2338170B1

公开(公告)日：2015-06-17

申请号：EP09785641.3

申请日：2009-09-14

申请人： Cambridge Silicon Radio Limited

发明人： HOLLAND, Andrew

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L24/94 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/12 ,  H01L24/17 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014

摘要： An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

公开(公告)号：EP1107307A4

公开(公告)日：2001-12-27

申请号：EP00935668

申请日：2000-06-13

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) is formed to have an opening (3a) corresponding to an electrode pad (2). A projection (4) of resin is then formed on the insulating layer (3). A resist layer is formed to have openings corresponding to the opening (3a), the projection (4) and the area between them. A Cu-plated layer (6) is formed by electrodeposition using the resist layer as a mask.

摘要翻译： 绝缘层（3）形成为具有对应于电极焊盘（2）的开口（3a）。 然后在绝缘层（3）上形成树脂突起（4）。 抗蚀剂层形成为具有对应于开口（3a），突起（4）和它们之间的区域的开口。 通过使用抗蚀剂层作为掩模的电沉积形成镀铜层（6）。

公开(公告)号：EP1107307A8

公开(公告)日：2001-11-21

申请号：EP00935668

申请日：2000-06-13

申请人： FUJIKURA LTD ,  TEXAS INSTRUMENTS JAPAN

发明人： SUZUKI TAKANAO ,  INABA MASATOSHI ,  OMINATO TADANORI ,  KAIZU MASAHIRO ,  KUROSAKA AKIHITO ,  SADAKATA NOBUYUKI ,  MASUMOTO MUTSUMI ,  MASUMOTO KENJI

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60 ,  H01L23/12

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.