公开(公告)号：EP2153511B1

公开(公告)日：2011-01-12

申请号：EP08746551.4

申请日：2008-04-22

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H02M1/42 ,  H02M3/157 ,  H03M3/04

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

公开(公告)号：EP3171514A1

公开(公告)日：2017-05-24

申请号：EP15195360.1

申请日：2015-11-19

申请人： NXP B.V.

发明人： Bajoria, Shagun ,  Bolatkale, Muhammed ,  Rutten, Robert ,  Breems, Lucien ,  Brekelmans, Johannes ,  Niehof, Jan

IPC分类号： H03F1/32 ,  H03F3/45 ,  H03K5/24

CPC分类号： H03D7/12 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45138 ,  H03M3/422 ,  H03M3/454 ,  H03M3/476

摘要： A summing node (200) is provided for summing a first (Vin+, Vin-) and second (Veld+,Veld-) differential signals. Each of the first and second differential signals comprise respective direct (Vin+, Veld+) and inverse (Vin-, Veld-) signal components. The summing node (200) comprises a first differential transistor pair (M1, M2) comprising a first (201a) and second (202a) input and coupled to a first (330) and second (340) output. The summing node (200) further comprises a second differential transistor pair (M3, M4) comprising a third (202b) and fourth (201b) input and coupled to the first (330) and second (340) output. The first (201a) and fourth (201b) inputs are respectively coupled to the direct (Vin+) and inverse (Vin-) signal components of the first differential signal and the second (202a) and third (202b) inputs are respectively coupled to the direct (Veld+) and inverse (Veld-) signal components of the second differential signal.

摘要翻译： 求和节点（200）被提供用于对第一（Vin +，Vin-）和第二（Veld +，Veld-）差分信号求和。 第一和第二差分信号中的每一个包括相应的直接（Vin +，Veld +）和反相（Vin-，Veld-）信号分量。 求和节点（200）包括包含第一（201a）和第二（202a）输入并且耦合到第一（330）和第二（340）输出的第一差分晶体管对（M1，M2）。 求和节点（200）还包括第二差分晶体管对（M3，M4），其包括第三（202b）和第四（201b）输入并且耦合到第一（330）和第二（340）输出。 第一（201a）和第四（201b）输入分别耦合到第一差分信号的直接（Vin +）和反相（Vin-）信号分量，并且第二（202a）和第三（202b）输入分别耦合到 直接（Veld +）和反向（Veld-）第二差分信号的信号分量。

公开(公告)号：EP1260039B1

公开(公告)日：2006-01-11

申请号：EP01924102.5

申请日：2001-02-28

申请人： GENERAL INSTRUMENT CORPORATION

发明人： HOWALD, Robert, L.

IPC分类号： H04B10/155 ,  H03M3/02 ,  H04N7/22

CPC分类号： H04N7/17309 ,  H03M3/424 ,  H03M3/476 ,  H04B10/25751 ,  H04B10/503 ,  H04B10/541 ,  H04N21/6118 ,  H04N21/6168

摘要： A system and method for increasing the performance of a digital return path in a hydrid-fiber-coax television system using baseband serial optical transport, receives an analog composite return path waveform at a comparator input to a digital return transmitter that includes an A/D converter and a first nonlinear processor. A first processing function is applied to signal output from the comparator at the first nonlinear processor and the processed signal is forwarded to the A/D converter which converts the processed signal to generate a quantized output signal of a sequence of digital words whose value represent analog signal samples. The quantized digital signal is output to an output of the digital return transmitter and to a feedback loop including a D/A converter, which converts the quantized digital signal to an analog feedback signal and forwards the analog feedback signal to a second processor. The second processor applies a second processing function to the analog feedback signal and outputs the processed analog feedback signal to the comparator input of the digital return transmitter. The comparator input to the digital return transmitter adds the processed analog feedback signal to the analog composite return path waveform to create the signal output from the comparator.

公开(公告)号：EP2151061B1

公开(公告)日：2017-10-18

申请号：EP08747478.9

申请日：2008-05-02

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H03M3/04

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

公开(公告)号：EP1260039A2

公开(公告)日：2002-11-27

申请号：EP01924102.5

申请日：2001-02-28

申请人： General Instrument Corporation

发明人： HOWALD, Robert, L.

IPC分类号： H04B10/155 ,  H03M3/02 ,  H04N7/22

CPC分类号： H04N7/17309 ,  H03M3/424 ,  H03M3/476 ,  H04B10/25751 ,  H04B10/503 ,  H04B10/541 ,  H04N21/6118 ,  H04N21/6168

摘要： A system and method for increasing the performance of a digital return path in a hydrid-fiber-coax television system using baseband serial optical transport, receives an analog composite return path waveform at a comparator input to a digital return transmitter that includes an A/D converter and a first nonlinear processor. A first processing function is applied to signal output from the comparator at the first nonlinear processor and the processed signal is forwarded to the A/D converter which converts the processed signal to generate a quantized output signal of a sequence of digital words whose value represent analog signal samples. The quantized digital signal is output to an output of the digital return transmitter and to a feedback loop including a D/A converter, which converts the quantized digital signal to an analog feedback signal and forwards the analog feedback signal to a second processor. The second processor applies a second processing function to the analog feedback signal and outputs the processed analog feedback signal to the comparator input of the digital return transmitter. The comparator input to the digital return transmitter adds the processed analog feedback signal to the analog composite return path waveform to create the signal output from the comparator.

公开(公告)号：EP3340474A1

公开(公告)日：2018-06-27

申请号：EP16205911.7

申请日：2016-12-21

申请人： Intel IP Corporation

发明人： DI GIANDOMENICO, Antonio ,  KAMPUS, Vahur

IPC分类号： H03M3/00 ,  H03M1/66

CPC分类号： H03M3/454 ,  H03M1/664 ,  H03M3/37 ,  H03M3/464 ,  H03M3/476

摘要： Analog-to-digital converter devices and methods are provided, where feedback using a nonlinear digital-to-analog converter is used. In some implementations, such a nonlinear digital-to-analog converter feedback may be used to compensate extra loop delay while maintaining stability and/or not injecting any additional noise.

公开(公告)号：EP2153513A1

公开(公告)日：2010-02-17

申请号：EP08747506.7

申请日：2008-05-02

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H02M3/156

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

公开(公告)号：EP2153512A2

公开(公告)日：2010-02-17

申请号：EP08747479.7

申请日：2008-05-02

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H02M1/42

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

摘要翻译： 功率因数校正（PFC）控制器和方法使用有限状态机来调节脉宽调制（PWM）切换控制信号的占空比。 PFC控制器具有目标电流发生器，其接收链路输出电压并产生与整流线路输入电压成比例的目标电流。 PFC控制器还包括输出双电平电流比较结果信号的比较器。 响应于两电平电流比较结果信号的有限状态机产生开关控制信号，该开关控制信号具有调节用于控制开关的占空比，使得感测到的电流与整流线路输入电压近似成比例，使得功率 进行因子校正。

公开(公告)号：EP2153511A1

公开(公告)日：2010-02-17

申请号：EP08746551.4

申请日：2008-04-22

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H02M1/42 ,  H02M3/157

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

公开(公告)号：EP2151061A1

公开(公告)日：2010-02-10

申请号：EP08747478.9

申请日：2008-05-02

申请人： Cirrus Logic, Inc.

发明人： MELANSON, John, L.

IPC分类号： H03M3/04

CPC分类号： H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

摘要： A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

摘要翻译： 功率因数校正（PFC）控制器和方法使用有限状态机来调节脉宽调制（PWM）切换控制信号的占空比。 PFC控制器具有目标电流发生器，其接收链路输出电压并产生与整流线路输入电压成比例的目标电流。 PFC控制器还包括输出双电平电流比较结果信号的比较器。 响应于两电平电流比较结果信号的有限状态机产生开关控制信号，该开关控制信号具有调节用于控制开关的占空比，使得感测到的电流与整流线路输入电压近似成比例，使得功率 进行因子校正。