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    MEMORY WITH FLY-BITLINES THAT WORK WITH SINGLE-ENDED SENSING AND ASSOCIATED MEMORY ACCESS METHOD
    1.
    发明公开
    MEMORY WITH FLY-BITLINES THAT WORK WITH SINGLE-ENDED SENSING AND ASSOCIATED MEMORY ACCESS METHOD 审中-公开

    公开(公告)号：EP4362017A1

    公开(公告)日：2024-05-01

    申请号：EP23200671.8

    申请日：2023-09-28

    申请人： MediaTek Inc.

    发明人： HONG, Chi-Hao

    IPC分类号： G11C7/06 ,  G11C7/18 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C7/18 ,  G11C7/067

    摘要： A memory includes a memory array and a single-ended sense amplifier circuit. The memory array includes wordlines, bitlines, and memory cells. The bitlines include a first bitline, routed on a first metal layer but not a second metal layer, and a second bitline, routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the wordlines. The memory cells include a first group of memory cells, coupled to the first bitline, and a second group of memory cells, coupled to the second bitline, where the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit performs a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled.

    "> THREE-DIMENSIONAL
    2.
    发明公开
    THREE-DIMENSIONAL "AND" FLASH MEMORY DEVICE 审中-公开

    公开(公告)号：EP4210060A1

    公开(公告)日：2023-07-12

    申请号：EP22152221.2

    申请日：2022-01-19

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yeh, Teng-Hao ,  Lue, Hang-Ting ,  Hsu, Tzu-Hsuan

    IPC分类号： G11C16/24 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C5/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

    摘要： A three-dimensional memory device (100, 200), such as 3D AND Flash memory device, includes a first page buffer (111, 211), a second page buffer (112, 212), a sense amplifier (130, 230), a first path selector (121, 221), and a second path selector (122, 222). The first page buffer (111, 211) and the second page buffer (112, 212) are respectively configured to temporarily store a first write-in data (WD1) and a second write-in data (WD2). The first path selector (121, 221) couples the sense amplifier (130, 230) or the first page buffer (111, 211) to a first global bit line (GBL1) according to a first control signal (CT1). The second path selector (122, 222) couples the sense amplifier (130, 230) or the second page buffer (112, 212) to a second global bit line (GBL2) according to a second control signal (CT2).

    BISTABLE CIRCUIT, ELECTRONIC CIRCUIT, STORAGE CIRCUIT, AND PROCESSING DEVICE
    3.
    发明公开
    BISTABLE CIRCUIT, ELECTRONIC CIRCUIT, STORAGE CIRCUIT, AND PROCESSING DEVICE 审中-公开

    公开(公告)号：EP4105932A1

    公开(公告)日：2022-12-21

    申请号：EP21753980.8

    申请日：2021-01-29

    申请人： Japan Science and Technology Agency

    发明人： SUGAHARA, Satoshi ,  SHIOTSU, Yusaku

    IPC分类号： G11C11/412 ,  G06F12/00 ,  G06N3/063 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18 ,  G11C14/00 ,  H03K3/356 ,  H03K3/3565

    摘要： A bistable circuit includes a first inverter circuit and a second inverter circuit each including a first FET having a channel of a first conductivity type, wherein a source of the first FET is coupled to a power supply line, a drain of the first FET is coupled to an intermediate node, and a gate of the first FET is coupled to an input node, a second FET having a channel of the first conductivity type, wherein a source of the second FET is coupled to the intermediate node, and a drain of the second FET is coupled to an output node, a third FET, wherein one of a source and a drain of the third FET is coupled to the intermediate node, and the other of the source and the drain of the third FET is coupled to a bias node, a fourth FET having a channel of a second conductivity type opposite to the first conductivity type, wherein one of a source and a drain of the fourth FET is coupled to the output node, and the other of the source and the drain of the fourth FET is coupled to a control line, a first memory node to which an input node of the first inverter circuit and an output node of the second inverter circuit are coupled, and a second memory node to which an output node of the first inverter circuit and an input node of the second inverter circuit are coupled, wherein gates of the fourth FETs of the first inverter circuit and the second inverter circuit are coupled to a word line, wherein a gate of the third FET of the first inverter circuit is coupled to one of the following nodes: the input node and the output node of the first inverter circuit and the input node and the output node of the second inverter circuit, and wherein a gate of the third FET of the second inverter circuit is coupled to one of the following nodes: the input node and the output node of the second inverter circuit and the input node and the output node of the first inverter circuit.

    INTERCONNECTION ARCHITECTURE FOR MULTILAYER CIRCUITS
    8.
    发明公开
    INTERCONNECTION ARCHITECTURE FOR MULTILAYER CIRCUITS 审中-公开
    连接多层电路结构

    公开(公告)号：EP2946385A4

    公开(公告)日：2016-10-19

    申请号：EP13871450

    申请日：2013-01-18

    申请人： HEWLETT PACKARD ENTPR DEV LP

    发明人： ROBINETT WARREN

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C13/00

    CPC分类号： G11C13/0026 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

    摘要： A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided.

    摘要翻译： 计算机可读存储器包括电路层，层叠在电路层上以形成存储盒的多层存储器，所述存储盒包括与电路层和四个侧表面接口的底表面;以及第一开关交叉开关串阵列， 侧面的记忆盒。 多个通孔将电路层连接到第一开关横截面层。 第一开关交叉开关串接受来自多个通孔的信号，并且将多层存储器中的交叉开关选择性地连接到电路层。 还提供了一种寻址多层存储器的方法。

    Systems and methods for dynamic power savings in electronic memory operation
    10.
    发明公开
    Systems and methods for dynamic power savings in electronic memory operation 审中-公开
    系统和Verfahrenfürdynamische Stromersparnisse beim elektronischen Speicherbetrieb

    公开(公告)号：EP2682943A1

    公开(公告)日：2014-01-08

    申请号：EP13186540.4

    申请日：2009-04-08

    申请人： Qualcomm Incorporated

    发明人： Rao, Hari ,  Park, Dongkyu ,  Abu-Rahma, Mohamed, Hassan

    IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12

    摘要： Power reduction is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, bit lines and/or word lines are segmented using latch repeaters to control address selection with respect to single-bit and/or single-word segments beyond a first single-bit and/or single-word segment. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles.

    摘要翻译： 通过分割存储器的部分并且仅根据存储器被访问的位置启用某些存储器部分，在电子存储器中实现功率降低。 在一个实施例中，使用锁存中继器对位线和/或字线进行分段，以控制超过第一单位和/或单字段的单位和/或单字段的地址选择。 在一个实施例中，在存储器读/写周期完成时，锁存中继器被允许保持在其操作/非操作状态。 这样就可以在连续周期访问相同的段时避免连续的使能脉冲。