公开(公告)号：EP4406371A1

公开(公告)日：2024-07-31

申请号：EP22873790.4

申请日：2022-09-16

申请人： Jabil Inc.

发明人： TIMMINS, Ian, Jeffery ,  RAFIE, Babak, Zarrin

IPC分类号： H05K1/02 ,  H01L23/28 ,  H01L23/40 ,  H01Q3/26 ,  H01Q13/02 ,  H01Q9/04 ,  H01L27/10 ,  H04W84/02

CPC分类号： H01L23/36 ,  H01Q21/0093 ,  H01Q21/065 ,  H01Q21/064 ,  H01L23/66 ,  H01L2223/667720130101 ,  H05K1/165 ,  H05K2201/1009820130101 ,  H05K1/0298

公开(公告)号：EP4060718B1

公开(公告)日：2023-12-06

申请号：EP21783125.4

申请日：2021-06-08

发明人： SU, Xingsong ,  BAI, Weiping ,  YU, Mengkang ,  WANG, Lianhong

IPC分类号： H01L21/31 ,  H01G4/10 ,  H01L27/10 ,  H10N97/00

公开(公告)号：EP3208832B1

公开(公告)日：2023-09-20

申请号：EP15850701.2

申请日：2015-10-06

发明人： TANIGUCHI, Yasuhiro ,  KAWASHIMA, Yasuhiko ,  KASAI, Hideo ,  SAKURAI, Ryotaro ,  SHINAGAWA, Yutaka ,  OKUYAMA, Kosuke

IPC分类号： H01L21/336 ,  H01L27/10 ,  H10B43/35 ,  H10B43/50 ,  H01L29/66 ,  H01L29/788

公开(公告)号：EP4160694A1

公开(公告)日：2023-04-05

申请号：EP22198944.5

申请日：2022-09-30

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： NIEBOJEWSKI, Heimanu ,  BEDECARRATS, Thomas ,  BERTRAND, Benoit

IPC分类号： H01L29/06 ,  H01L27/10 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00

摘要： L'invention concerne un procédé de fabrication d' un circuit électronique quantique comprenant une couche semi-conductrice destinée à recevoir des qubits dans des îlots quantiques. La couche qubits peut recevoir les qubits pendant leur stockage et leur manipulation.Un aspect de l'invention concerne un procédé de fabrication d'un circuit (DISP) électronique quantique comprenant les étapes suivantes :
- graver une couche semiconductrice de manière à obtenir :
- une pluralité de piliers (PLR) chaque pilier semi-conducteur présentant une première extrémité, dite "base"; et
- une couche qubits (QBL) à la base de chaque pilier semiconducteur ;;

- oxyder le flanc de chaque pilier (PLR) ;
- former des lignes de couplage (CL) et des colonnes de couplage (CC) ; et
- déposer des couches de séparation (SEP1, SEP2, SEP3) en laissant dépasser une surface de contact (CS) de chaque pilier (PLR).

公开(公告)号：EP4020599A2

公开(公告)日：2022-06-29

申请号：EP21194481.4

申请日：2021-09-02

申请人： INTEL Corporation

发明人： SEN GUPTA, Arnab ,  ALAAN, Urusa ,  WEBER, Justin ,  KUO, Charles C. ,  CHEN, Yu-Jin ,  OGUZ, Kaan ,  METZ, Matthew V. ,  SHARMA, Abhishek A. ,  MAJHI, Prashant ,  DOYLE, Brian S. ,  LE, Van H.

IPC分类号： H01L29/872 ,  H01L29/24 ,  H01L29/66 ,  H01L27/10 ,  H01L27/24

摘要： Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：EP3264464B1

公开(公告)日：2021-12-22

申请号：EP16755350.2

申请日：2016-02-19

发明人： KASAI Hideo ,  TANIGUCHI Yasuhiro ,  KAWASHIMA Yasuhiko ,  SAKURAI Ryotaro ,  SHINAGAWA Yutaka ,  TOYA Tatsuro ,  YAMAGUCHI Takanori ,  OWADA Fukuo ,  YOSHIDA Shinji ,  HATADA Teruo ,  NODA Satoshi ,  KATO Takafumi ,  MURAYA Tetsuya ,  OKUYAMA Kosuke

IPC分类号： H01L27/10 ,  G11C17/16 ,  H01L27/112 ,  H01L23/525

公开(公告)号：EP3633724B1

公开(公告)日：2021-04-21

申请号：EP19199720.4

申请日：2019-09-26

发明人： ERLBACHER, Tobias

IPC分类号： H01L27/10 ,  H01L29/66 ,  H01L29/94 ,  H01L21/78 ,  H01L23/64 ,  H01L27/02

公开(公告)号：EP3780073A1

公开(公告)日：2021-02-17

申请号：EP19785253.6

申请日：2019-04-08

申请人： Hitachi High-Tech Corporation

发明人： IKEDA Ukyo ,  ONO Tetsuyoshi ,  NAKATSUCHI Hiroki ,  MIYAKE Masafumi

IPC分类号： H01L21/56 ,  G01N27/333 ,  G06K19/00 ,  H01L23/28 ,  H01L27/10

摘要： An electrode formed by molding a semiconductor device with resin. The electrode comprises: a first resin mold portion formed on a front surface of the semiconductor device and having a first thickness (t1) ; a second resin mold portion formed on a back surface of the semiconductor device and having a second thickness (t2) greater than the first thickness; and an exposed portion formed in a part of the first resin mold portion corresponding to an end of the semiconductor device.

公开(公告)号：EP3300111B1

公开(公告)日：2021-02-17

申请号：EP16827814.1

申请日：2016-07-21

发明人： YOSHIDA Shoji ,  OWADA Fukuo ,  OKADA Daisuke ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  YANAGISAWA Kazumasa ,  TANIGUCHI Yasuhiro

IPC分类号： H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28

公开(公告)号：EP3550604A1

公开(公告)日：2019-10-09

申请号：EP19156160.4

申请日：2010-12-01

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  KATO, Kiyoshi

IPC分类号： H01L27/105 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  G11C16/04 ,  G11C16/26 ,  H01L27/118

摘要： The invention is directed to a memory device comprising: a memory cell, wherein the memory cell comprises a first transistor and a second transistor, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a reading circuit through a wiring, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor, wherein a gate electrode of the second transistor is electrically connected to a signal line, wherein the first transistor comprises a first oxide semiconductor layer in a channel formation region, and wherein the second transistor comprises a second oxide semiconductor layer in a channel formation region.