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    VERTICAL MEMORY DEVICE
    1.
    发明公开
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：EP4105992A3

    公开(公告)日：2023-02-08

    申请号：EP22178985.2

    申请日：2022-06-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： KWON, Yongseok ,  RHO, Youngsik ,  PARK, Sangwon ,  SEO, Sungwhan ,  LEE, Dongkyu ,  JEONG, Jaeyong

    IPC分类号： H01L27/11578 ,  H01L27/11526 ,  H01L25/065 ,  H01L23/00 ,  H01L49/02

    摘要： A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    4.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 审中-公开

    公开(公告)号：EP3945584A2

    公开(公告)日：2022-02-02

    申请号：EP21188820.1

    申请日：2021-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： YOUNG, Bo-Feng ,  YEONG, Sai-Hooi ,  CHUI, Chi On ,  LIN, Yu-Ming

    IPC分类号： H01L27/11578 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

    摘要： 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.