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    Memory device
    61.
    发明专利
    Memory device 审中-公开

    公开(公告)号：JP2004310650A

    公开(公告)日：2004-11-04

    申请号：JP2003106360

    申请日：2003-04-10

    Applicant: Renesas Technology Corp ,  株式会社ルネサステクノロジ

    Inventor： SHINAGAWA CHIAKI ,  SHIRAISHI ATSUSHI ,  KANAMORI SAKAKI

    IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02 ,  G06K19/07 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3495 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/349

    Abstract: PROBLEM TO BE SOLVED: To preliminarily prevent any accident to change data due to the accumulated influence of disturbance in a memory area which rewriting dose not generate is prevented beforehand. SOLUTION: A memory device comprises an erasable and writable nonvolatile memory (2) and a control circuit (5). The control circuit is made possible to perform the replacing processing of a memory area in a predetermined timing. The replacing processing is performed by writing the stored data of a first memory area, which has relatively a fewer number of times of rewrite, in a second memory area which is not used and replaces the first memory area with the second memory area, where the data has been written, as a working area. Thus, a memory area which has a fewer number of times of rewrite is used as an object to be replaced with another memory area so that it is possible to preliminarily prevent any accident to change illegal data due to the accumulated influence of disturbance in a memory area which has no rewrite. COPYRIGHT: (C)2005,JPO&NCIPI

    Nonvolatile semiconductor memory
    64.
    发明专利
    Nonvolatile semiconductor memory 有权

    公开(公告)号：JP2004014043A

    公开(公告)日：2004-01-15

    申请号：JP2002167314

    申请日：2002-06-07

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： SUGIURA YOSHIHISA ,  SUZUKI TAKASHI

    IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C27/00

    CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C27/005

    Abstract: PROBLEM TO BE SOLVED: To perform rewriting control with a small number of circuits by storing the number of times of rewriting in a memory element analogically in a NAND type flash memory. SOLUTION: This memory is provided with a memory cell array 10 divided into a plurality of parts, and a rewriting number of times writing control circuit in which writing is performed for a cell transistor of the rewriting number of times storing region 10 allotted to a portion in non-selection arrays out of a plurality of memory cell arrays with a weaker electric field than that for normal writing, and the number of times of rewriting is stored by varying analogically a threshold of the cell transistor by the quantity of injection of electrons to a floating gate of the cell transistor. COPYRIGHT: (C)2004,JPO

    Non-volatile memory device
    66.
    发明专利
    Non-volatile memory device 失效
    非易失性存储器件

    公开(公告)号：JPS58215794A

    公开(公告)日：1983-12-15

    申请号：JP9830782

    申请日：1982-06-08

    Applicant: Toshiba Corp

    Inventor： TANAKA NORIYUKI

    IPC: H01L27/10 ,  G11C16/02 ,  G11C16/34 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/3495 ,  G11C16/349

    Abstract: PURPOSE:To decrease the number of times of replacement of a memory and to improve the reliability, by splitting a non-volatile memory having a storage capacity of plural times of that of a system to each block and providing an exclusive location of the number of times of write for each unit block. CONSTITUTION:A storage area of an EEPROM having a capacity >=2 times the capacity requested to the system is splitted to blocks 1 and 2, and the direction of split is taken in the direction of word arrangement. Exclusive locations 3, 4 to store the number of times of program write to the corresponding memory are allocated to the blocks 1, 2 respectively, and the number of bits of each location corresponds to the limit value of the number of times of program write of the corresponding memory. When the number of times of program write of the block 1 reaches a specified value, the block is used switchingly. Whether or not the number of times of write reaches the specified value is discriminated with a count value stored to the locations 3, 4.

    Abstract translation: 目的：为了减少更换存储器的次数并提高可靠性，通过将具有系统的多倍的存储容量的非易失性存储器分割成每个块并提供数量的独占位置 每个单位块的写入次数。 构成：具有容量> =系统要求的容量的2倍的EEPROM的存储区域被分割成块1和2，并且沿字排列的方向获取分割的方向。 将存储对相应存储器的程序写入次数的独占位置3,4分别分配给块1,2，并且每个位置的位数对应于程序写入次数的极限值 相应的内存。 当块1的程序写入次数达到指定值时，该块被切换使用。 写入次数达到规定值是否与存储在位置3,4的计数值进行区别。

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