公开(公告)号：JP2004041872A

公开(公告)日：2004-02-12

申请号：JP2002200820

申请日：2002-07-10

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： HANADA TAKEAKI ,  SAKUMA SHUICHI ,  YAMAUCHI SHIRO ,  YASUDA KENICHI ,  NAGAO EIICHI ,  ABE TETSUYA

IPC: B01D53/26

Abstract: PROBLEM TO BE SOLVED: To obtain a humidity controller capable of reducing the lowering of dehumidification efficiency with time. SOLUTION: The humidity controller is equipped with a solid electrolyte film 4 comprising a hydrogen ion conductive substance, catalyst-containing cathodic catalyst beds 5a and 5b provided on the surface of the solid electrolyte film 4 on the cathode side thereof, a first feeder 7 comprising a porous base material provided in contact with the cathodic catalyst beds 5a and 5b, the catalyst-containing anodic catalyst bed 2 provided on the surface of the solid electrolyte film 4 on the anode side thereof and a second feed body 1 comprising a porous substrate provided in contact with the anodic catalyst bed 2. The catalytic layers 5a and 5b are formed by containing a hydrogen conductive polymer. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003022698A

公开(公告)日：2003-01-24

申请号：JP2001208112

申请日：2001-07-09

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： YASUDA KENICHI

IPC: G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/12 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory provided with a test mode in which an abnormality in input capacity can be detected without directly measuring the input capacity with a measuring device.
SOLUTION: An input buffer circuit 21 includes a differential circuit consisting of P channel MOS transistors 211-213, N channel MOS transistors 214, 215, and a threshold value changing circuit consisting of P channel MOS transistors 217, 218. In the input buffer circuit 21, the threshold value changing circuit is activated at the time of a test mode, current quantity of the N channel MOS transistor 215 is increased, voltage of a node N1 is increased, and the reference voltage VREF is changed equivalently. And, the input buffer circuit 21 compares input voltage DIN of write-in data with the reference voltage VREF, and outputs output data in accordance with the comparison result to an internal circuit.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种具有测试模式的半导体存储器，其中可以在不用测量装置直接测量输入容量的情况下检测输入容量的异常。 解决方案：输入缓冲电路21包括由P沟道MOS晶体管211-213，N沟道MOS晶体管214,215和由P沟道MOS晶体管217,218组成的阈值变化电路构成的差分电路。在输入缓冲电路 如图21所示，阈值改变电路在测试模式时被激活，N沟道MOS晶体管215的电流量增加，节点N1的电压增加，参考电压VREF等效地改变。 并且，输入缓冲器电路21将写入数据的输入电压DIN与参考电压VREF进行比较，并将输出数据根据比较结果输出到内部电路。

公开(公告)号：JP2006233249A

公开(公告)日：2006-09-07

申请号：JP2005047244

申请日：2005-02-23

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： MITSUTA KENRO ,  YAMAUCHI SHIRO ,  TSUSHIMA HIROYUKI ,  YASUDA KENICHI ,  HARA KATSUNORI

IPC: C25B9/00 ,  B01D53/26 ,  B01D53/32 ,  C25B9/10 ,  C25B13/04

Abstract: PROBLEM TO BE SOLVED: To provide a production method where an electrochemical element capable of directly collecting current from an anode and a cathode while highly holding current efficiency is obtained without using an electrode base material, and also, the electrochemical element can be efficiently produced. SOLUTION: The solid high polymer electrolyte 4 is composed of two solid high polymer electrolytic membranes, and, for increasing the electric resistance of the extension part 41 therein, includes an electrically insulating film 5 between the two solid high polymer electrolytic membranes. Since the electrically insulating film 5 shields or at least reduces the electric current flowing through a non-electrolyzing region 6, high current efficiency can be held even in an electrolyzing region 7 even without using an electrode base material used in the conventional technique. Further, the electrically insulating film 5 has a film width at which the tip part enters a part of the electrolyzing region 7. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种能够在不使用电极基材的情况下获得能够直接从阳极和阴极收集电流而同时高效保持电流效率的生产方法，并且电化学元件可以 有效地生产。 解决方案：固体高分子电解质4由两个固体高分子电解质膜组成，为了增加其中的延伸部分41的电阻，在两个固体高分子电解质膜之间包括电绝缘膜5。 由于电绝缘膜5屏蔽或至少减小了流过非电解区域6的电流，所以即使不使用传统技术中使用的电极基材，也可以在电解区域7中保持高的电流效率。 此外，电绝缘膜5具有尖端部分进入电解区域7的一部分的膜宽度。版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004041871A

公开(公告)日：2004-02-12

申请号：JP2002200819

申请日：2002-07-10

Applicant: Mitsubishi Electric Corp ,  三菱電機株式会社

Inventor： NAGAO EIICHI ,  SAKUMA SHUICHI ,  YAMAUCHI SHIRO ,  YASUDA KENICHI ,  HANADA TAKEAKI ,  ABE TETSUYA

IPC: B01D53/26

Abstract: PROBLEM TO BE SOLVED: To obtain a humidity regulator having improved dehumidification performance. SOLUTION: This humidity regulator is provided with an electrochemical element 2 which consists of a solid electrolytic membrane consisting of a cation-conductive substance, a first catalyst layer arranged on the side of the atmosphere to be dehumidified of the solid electrolytic membrane, a second catalyst layer arranged on the side open to the atmosphere of the solid electrolytic membrane and a first and a second porous base materials abutted on the first and second catalyst layers respectively as power feeding bodies. A fan 7 is arranged on the dehumidification side 6 of the element 2 for generating a rising air current. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000030448A

公开(公告)日：2000-01-28

申请号：JP20065598

申请日：1998-07-15

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： ARAKI TAKESHI ,  YASUDA KENICHI

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To suppress the increase of a chip area by generating timing control signals of memory cell blocks which are selected by delaying external control signals and controlling operations of corresponding memory cell blocks by plural block controlling means in accordance with these timing control signals to suppress areas of regions of delay circuits. SOLUTION: An SDRAM 1000 is provided with a control signal generating circuit 32 generating various kinds of internal control signals ϕRBB0, 1 to ϕSEE. The circuit 32 is provided with only one delay control signal generating circuit generating delay signals needed for generating control signals controlling activations and inactivations of banks A0 to B1 and is shared with respect to banks A0 to B1. Moreover, bank control signal generating circuits 200.1-2 which consist of SR flip-flop circuits and whose regions are small are provided in the respective banks A0 to B1. Thus, the increasing of the chip area is suppressed in the constitution of plural banks like this SDRAM 1000.

公开(公告)号：JPH11353228A

公开(公告)日：1999-12-24

申请号：JP16200098

申请日：1998-06-10

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： KUBO TAKASHI ,  YASUDA KENICHI ,  IWAMOTO HISASHI

IPC: G06F12/06 ,  G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To provide a memory module system which can increase the capacity of a memory module while maintaining high-speed data transfer. SOLUTION: This system is equipped with a memory controller, the memory module, and an external data bus 2 which is provided in common to memory modules. The memory module is equipped with memory chips 11, internal data buses 12 connected between corresponding memory chips 11 and input/output terminals 10, a logic chip 13, and switch transistors 14 which turn on and off in response to a switch control signal SWCTL from the logic chip 13. In this constitution, only a selected memory module is connected to the external data bus. Therefore, even if memory modules increase in number, the load on the external data bus does not increase, high-speed data transfer can be maintained, and the capacity of the memory module can be increased.

公开(公告)号：JPH10228797A

公开(公告)日：1998-08-25

申请号：JP21467697

申请日：1997-08-08

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： TANAKA SHINJI ,  TANAKA KOJI ,  ASAKURA MIKIO ,  YASUDA KENICHI

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which data can be written in all normal memory cells even after rewriting in a redundant memory cell is performed. SOLUTION: This device is provided with a normal column selecting signal switching means 20 switching a signal outputted by a normal column selecting signal generation means 19 in accordance with a test mode signal TMC1. Even when the normal column selecting signal generation means 19 outputs a signal making a normal column decoder 3 a disable state, the normal column selecting signal switching means 20 switches the signal and makes the normal column decoder 3 an active state at the time of a test.

公开(公告)号：JPH09148540A

公开(公告)日：1997-06-06

申请号：JP30886595

申请日：1995-11-28

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： YASUDA KENICHI ,  HIDAKA HIDETO ,  ASAKURA MIKIO ,  OISHI TSUKASA ,  HAMAIDE HIROSHI

IPC: H01L21/66 ,  G11C29/00 ,  G11C29/56 ,  H01L21/60 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/50 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device provided with pad arrangement wherein the number of pads can be easily increased, testing is facilitated, and internal potential is stabilized. SOLUTION: Pads PD are arranged in order in the central part region CR of a semiconductor chip 1. Pads P1-P4 are arranged in the outer peripheral part of the central part of the chip 1. The pad P1 of the outer peripheral part is electrically connected with a die pad 10 on which a semiconductor chip is mounted via insulating material 12. Electric potential applied to the pad 1 of the outer peripheral part can be stabilized by a parasitic capacitance of the die pad 10. By notching a part of mold resin after resin molding, the potential of the die pad 10 can be easily monitored from the outside.

公开(公告)号：JPH07122645A

公开(公告)日：1995-05-12

申请号：JP16561094

申请日：1994-07-18

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： TANAKA KOJI ,  MIYAMOTO HIROSHI ,  YASUDA KENICHI ,  KIKUTA SHIGERU

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: PURPOSE:To allow easy formation of a contact hole even when the height from the surface of a semiconductor substrate to the upper surface of an interlayer insulation film increases due to high integration of a semiconductor device. CONSTITUTION:A wiring pad 12a is formed on an N well potential fixed region 6 and a contact hole 13c is made through an interlayer insulation film 13 deposited thereon.

公开(公告)号：JPH05167155A

公开(公告)日：1993-07-02

申请号：JP32766491

申请日：1991-12-11

Applicant: MITSUBISHI ELECTRIC CORP

Inventor： MINEOKA KEIZOU ,  YASUDA KENICHI ,  YABUUCHI MASATAKA ,  ETO NOBUO

IPC: H01S3/09 ,  H01S3/097 ,  H03K17/04

Abstract: PURPOSE:To supply uniform gate currents to semiconductor elements and to substantially simultaneously set timings of gate ON thereof by providing a switch element for discharging a gate current to be supplied with a gate current to a semiconductor element group provided at each semiconductor element block and disposed at an equal distance therefrom. CONSTITUTION:A gate driving circuit 1A drives a semiconductor element group 5A having a plurality of intrinsic semiconductor element block 9 having a plurality of semiconductor elements 15 connected in parallel. The circuit 1A has a gate pulse signal amplifier 6, and a switch element 3A for discharging a gate current to be supplied with a gate current to the element 15 at each block 9. The element 3A is so disposed that the lengths of all the wirings in which the gate currents flow substantially constant for the block 9. Thus, substantially uniform gate currents flow to the gates of the elements 15 to set the timings of gate ON substantially at the same time.