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公开(公告)号：JP2007201236A
公开(公告)日：2007-08-09
申请号：JP2006018876
申请日：2006-01-27
发明人： OZAWA OSAMU , SASAKI TOSHIO , MORI RYO , KURAISHI TAKASHI , YASU YOSHIHIKO
IPC分类号： H01L21/8234 , H01L21/822 , H01L27/04 , H01L27/088 , H01L29/786
CPC分类号： H01L29/7841 , H01L27/1203 , H01L29/78615 , H03F1/0205 , H03F1/301 , H03F2200/513 , H03K19/0016 , H03K19/00338 , H03K19/00384 , H03K19/01707
摘要： PROBLEM TO BE SOLVED: To increase operation speed and reduce power consumption in a circuit using an SOI-type MOS transistor. SOLUTION: In a plurality of MOS transistors of an SOI structure, body floating, a fixed body voltage, and a variable body voltage are combined. The body floating, body fixed voltage, and variable body bias may be adopted for cases where high-speed operation is expected in a logical circuit mainly composed of switching operation while an operating power supply is at a relatively low voltage, the kink phenomenon of current/voltage characteristics is hated essentially as in an analog-based circuit, and high-speed operation is required in an active state and low power consumption is required in a standby state as in a logical circuit, respectively. By combining the body floating, fixed body voltage, and variable body voltage transistors, an accurate body bias can be adopted according to the functions and configurations of the circuit for high-speed operation and low power consumption. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译： 要解决的问题：提高使用SOI型MOS晶体管的电路的运行速度和降低功耗。 解决方案：在SOI结构的多个MOS晶体管中，组合体浮动，固定体电压和可变体电压。 在工作电源处于相对低电压的主要由开关操作组成的逻辑电路中预期高速运行的情况下，可以采用主体浮动，车体固定电压和可变体偏置，电流的扭结现象 /电压特性基本上如在基于模拟的电路中那样讨厌，而在活动状态下需要高速运行，并且在待机状态下分别需要在逻辑电路中低功耗。 通过组合主体浮动，固定体电压和可变体电压晶体管，可以根据电路的功能和配置采用精确的体偏置，实现高速运行和低功耗。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2008218722A
公开(公告)日：2008-09-18
申请号：JP2007054323
申请日：2007-03-05
发明人： FUKUOKA KAZUKI , SASAKI TOSHIO , OZAWA OSAMU , KURAISHI TAKASHI , YASU YOSHIHIKO
IPC分类号： H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To shorten activation time while suppressing the occurrence of power supply noises. SOLUTION: There are provided circuit blocks (12, 13, 14) which operate upon supplied power source, power switches (22, 23, 24) which can supply source to corresponding circuit blocks, and power supply switch controllers (32, 33, 34) capable of controlling the operation of the power supply switches. There are also provided a rush current monitor circuit (15) capable of monitoring rush currents for each of the circuit blocks when power supply is restored, and a setting part (17) capable of setting a drive timing of the power supply switches based on the rush current monitoring result of the rush current monitoring circuit. The power supply switch drive timing is optimized by allowing adjustment of power supply switch drive time based on the actual measurement result of rush currents for each circuit block. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译： 要解决的问题：在抑制电源噪声的发生的同时缩短激活时间。 解决方案：提供在所提供的电源上操作的电路块（12,13,14），可以向相应的电路块供电的电源开关（22,23,24）和电源开关控制器（32， 33,34）能够控制电源开关的操作。 还提供了一种冲击电流监视电路（15），其能够在电源恢复时监视每个电路块的冲击电流，并且能够基于该电源切换设置电源的驱动定时的设定部（17） 冲击电流监测电路的冲击电流监测结果。 通过根据每个电路块的冲击电流的实际测量结果调整电源开关驱动时间，优化电源开关驱动时序。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2010097470A
公开(公告)日：2010-04-30
申请号：JP2008268521
申请日：2008-10-17
发明人： SHOJIMA YUSUKE , KURAISHI TAKASHI
IPC分类号： G06F15/78
摘要： PROBLEM TO BE SOLVED: To make an external terminal for specifying an operation mode sufficiently function as a power supply terminal or a ground terminal and to easily switch the logic of the external terminal from the external. SOLUTION: A microcomputer includes: internal circuits (102-107), a ground line (29), a power supply line (28), external terminals (20, 21) for specifying the operation modes of the internal circuits (102-107), and a power supply switch circuit (101). The power supply switch circuit (101) includes a first power supply driver (40) for connecting the external terminals (20, 21) to the power supply line (28) or the ground line (29) and a second power supply driver (41) having a driving capacity smaller than that of the first power supply driver (40) to connect the external terminals (20, 21) to the power supply line (28) or the ground line (29). During the reset period of the internal circuits (102-107), the circuit operation of the first power supply driver (40) is inhibited, and after releasing the reset of the internal circuits (102-107), the circuit operation of the first power supply driver (40) is permitted. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译： 要解决的问题：使用于指定操作模式的外部端子充分地用作电源端子或接地端子，并且容易地从外部切换外部端子的逻辑。
方案：一种微型计算机包括：内部电路（102-107），接地线（29），电源线（28），外部端子（20,21），用于指定该内部电路的操作模式（102 -107）和电源开关电路（101）。 所述电源开关电路（101）包括用于与外部端子（20,21）连接到所述电源线（28）或与接地线（29）和第二电源驱动器的第一电源驱动器（40）（41 ）具有小于第一电源驱动器（40）的驱动能力以将外部端子（20,21）连接到电源线（28）或接地线（29）。 在内部电路的复位周期（102-107），所述第一电源驱动器的电路操作（40）被抑制，并释放内部电路的复位（102-107），所述第一的电路动作后 电源驱动器（40）被允许。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2007259005A
公开(公告)日：2007-10-04
申请号：JP2006079977
申请日：2006-03-23
IPC分类号： H03K19/0185 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To achieve a high speed charge-discharge operation of a level up shifter an output node and a low input voltage, and prevent the unstable propagation.
SOLUTION: When a first MOS transistor (MR1) connected to the drain of an output terminal (LSOUT) is set off, and a first MOS transistor (ML1) at the opposite side is set on; a sixth MOS transistor (MR6) is set on, by an inverting signal of a differential input signal at the output side, a seventh MOS transistor (MR7) keeps set on, and a fifth MOS transistor (MR5) keeps set off at an output terminal until this terminal is charged up to a specified level, a third MOS transistor (MR3) set on in this while making up for the charging operation by a second MOS transistor (MR2). When the output terminal is charged up to the specified level; the seventh MOS transistor (MR7) is set off, the fifth MOS transistor (MR5) is set on, and the third MOS transistor (MR3) is set off to end the supplementing charging operation.
COPYRIGHT: (C)2008,JPO&INPIT摘要翻译： 要解决的问题：为了实现电平转换器输出节点和低输入电压的高速充放电操作，并且防止不稳定的传播。 解决方案：当连接到输出端子（LSOUT）的漏极的第一MOS晶体管（MR1）被置位时，并且相对侧的第一MOS晶体管（ML1）被置为ON; 第六MOS晶体管（MR6）由输出侧的差分输入信号的反相信号置位，第七MOS晶体管（MR7）保持置ON，第五MOS晶体管（MR5）在输出端保持置位 端子，直到该端子被充电到指定电平为止，在通过第二MOS晶体管（MR2）补充充电操作的同时，第三MOS晶体管（MR3）置于此状态。 当输出端子充电到指定电平时; 第七MOS晶体管（MR7）被置位，第五MOS晶体管（MR5）置为ON，第三MOS晶体管（MR3）被置位以结束补充充电操作。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2007201414A
公开(公告)日：2007-08-09
申请号：JP2006249369
申请日：2006-09-14
发明人： OZAWA OSAMU , SASAKI TOSHIO , MORI RYO , KURAISHI TAKASHI , YASU YOSHIHIKO , ISHIBASHI KOICHIRO
IPC分类号： H01L29/786 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H03K19/00
CPC分类号： H01L27/1203 , H01L21/823857
摘要： PROBLEM TO BE SOLVED: To realize power-interrupting control having a high degree of freedom corresponding to an element separation structure that an SOI-type semiconductor integrated circuit has originally. SOLUTION: The semiconductor integrated circuit comprises a plurality of so-called SOI-type first MOS transistors MNtk, MPtk and second MOS transistors MNtn, MPtn. The first MOS transistor has a thicker gate insulating film than the second MOS transistor. The first MOS transistor and the second one compose a power-interruptible circuit 6 and a power non-interruptible circuit 7. The power-interruptible circuit has a first MOS transistor for composing a power switch 10 between power supply wiring VDD and ground wiring VSS, and a second MOS transistor connected to the first MOS transistor in series. The amplitude of the gate control signal in the first MOS transistor for composing the power switch is made larger than the gate control signal of the second MOS transistor. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译： 要解决的问题：实现与SOI型半导体集成电路原来的元件分离结构相对应的具有高自由度的功率中断控制。 解决方案：半导体集成电路包括多个所谓的SOI型第一MOS晶体管MNtk，MPtk和第二MOS晶体管MNtn，MPtn。 第一MOS晶体管具有比第二MOS晶体管更厚的栅绝缘膜。 第一MOS晶体管和第二MOS晶体管组成电源中断电路6和功率不可中断电路7.功率可中断电路具有第一MOS晶体管，用于在电源布线VDD和接地布线VSS之间组成电源开关10， 以及与第一MOS晶体管串联连接的第二MOS晶体管。 用于构成功率开关的第一MOS晶体管中的栅极控制信号的幅度大于第二MOS晶体管的栅极控制信号。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2007201853A
公开(公告)日：2007-08-09
申请号：JP2006018517
申请日：2006-01-27
发明人： OZAWA OSAMU , KURAISHI TAKASHI , SASAKI TOSHIO , FUKUOKA KAZUKI , YASU YOSHIHIKO
IPC分类号： H03K3/356 , H01L21/822 , H01L27/04 , H03K3/037 , H03K19/094
摘要： PROBLEM TO BE SOLVED: To optimize body bias control to a data holding flip-flop using an SOI type MOS transistor according to its operating state. SOLUTION: Each of a plurality of circuits consisting of the SOI type MOS transistor has a flip-flop consisting of a master latch part (MLAT) made into selective power shutdown by a power switch (10) and a slave latch part (SLATdr) made into non-object for the selective power shutdown. The slave latch part is body bias controlled so that threshold voltage of the MOS transistor may become small in a power non-shutdown state and body bias controlled so that the threshold voltage of the MOS transistor may become large in a power shutdown state. Thus, speeding up of the flip-flop is assured in the power non-shutdown state and subthreshold leak current at the slave latch part is reduced in an operation power source shutdown state of the master latch part. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译： 要解决的问题：根据其工作状态，使用SOI型MOS晶体管优化对数据保持触发器的体偏置控制。 解决方案：由SOI型MOS晶体管组成的多个电路中的每一个具有触发器，该触发器由通过电源开关（10）和从锁存器部分（10）形成选择性停电的主锁存部分（MLAT） SLATdr）成为非对象，用于选择性停电。 从锁存部分被控制为主体偏置，使得MOS晶体管的阈值电压在功率非关断状态下可能变小，并且控制体偏置，使得MOS晶体管的阈值电压在功率关闭状态下可能变大。 因此，在电源非关断状态下确保触发器的加速，并且在主锁存部分的操作电源关闭状态中从属锁存部分的次阈值泄漏电流减小。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2005311622A
公开(公告)日：2005-11-04
申请号：JP2004124683
申请日：2004-04-20
IPC分类号： H01L21/822 , G11C5/00 , G11C5/14 , H01L27/04 , H03K19/00 , H03K19/0175
CPC分类号： G11C5/147
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of attaining multifunctional capability and low power consumption with a simple constitution, and also, capable of improving design efficiency. SOLUTION: The semiconductor integrated circuit device has a first or third circuit block. The device is made into a first power supply state that the operation of an internal circuit is guaranteed in the first circuit block, and a second power supply state that the operation of the internal circuit is not guaranteed corresponding to instructions from the third circuit block. An input for receiving a signal outputted from the first circuit block is provided to a second circuit block. The device is provided with an input circuit, which maintains a specific signal level corresponding to an operating voltage of the second circuit block irrelevant to the signal outputted from the first circuit block in accordance with a control signal corresponding when the second power supply state is instructed to the first circuit block from the third circuit block. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译： 要解决的问题：提供一种能够以简单的结构实现多功能能力和低功耗的半导体集成电路器件，并且还能够提高设计效率。 解决方案：半导体集成电路器件具有第一或第三电路块。 该装置被制成第一电源状态，即在第一电路块中保证内部电路的操作，以及第二电源状态，内部电路的操作不能相应于来自第三电路块的指令被保证。 用于接收从第一电路块输出的信号的输入被提供给第二电路块。 该装置设置有输入电路，该输入电路根据在指示第二电源状态时对应的控制信号，保持对应于与第一电路块输出的信号无关的第二电路块的工作电压的特定信号电平 到第三电路块的第一电路块。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2005286675A
公开(公告)日：2005-10-13
申请号：JP2004097440
申请日：2004-03-30
IPC分类号： H03K19/003 , H03K17/22 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device adaptable to a plurality of power supply voltages and arranged to perform stable operation regardless of its throw-in order.
SOLUTION: A level shift circuit operates an internal circuit on a first power supply voltage, operates a plurality of I/O circuits on a plurality of power supply voltages higher than the first power supply voltage, and converts a signal amplitude corresponding to the first power supply voltage into a signal amplitude corresponding to each power supply voltage. A plurality of power supply detection circuits form a first control signal until the first power supply voltage and the plurality of power supply voltages reach predetermined levels, respectively, and control a corresponding I/O circuit to a predetermined operating state. That I/O circuit is then controlled to that predetermined operating state by a third control signal being fed from an external terminal through an input buffer operating on any one of the plurality of power supply voltages.
COPYRIGHT: (C)2006,JPO&NCIPI摘要翻译： 要解决的问题：提供一种适用于多个电源电压的半导体集成电路装置，并且被布置为执行稳定的操作，而不管其投放顺序如何。 解决方案：电平移位电路以第一电源电压操作内部电路，在高于第一电源电压的多个电源电压上操作多个I / O电路，并将对应于 将第一电源电压变为对应于每个电源电压的信号幅度。 多个电源检测电路形成第一控制信号，直到第一电源电压和多个电源电压分别达到预定电平，并将相应的I / O电路控制到预定的工作状态。 然后通过从外部端子通过在多个电源电压中的任何一个上操作的输入缓冲器馈送的第三控制信号将该I / O电路控制到该预定操作状态。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2005286082A
公开(公告)日：2005-10-13
申请号：JP2004097428
申请日：2004-03-30
IPC分类号： H01L21/822 , G06F1/00 , H01L23/522 , H01L27/02 , H01L27/04 , H03K17/687 , H03K19/00
CPC分类号： H01L27/0207 , H01L23/5223 , H01L24/06 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H03K17/6871 , H03K19/0016 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device where design efficiency is improved, while realizing attainment of enhanced functions. SOLUTION: An inner circuit is surrounded by a first cell, where a first switching element connecting a power voltage line or a ground line with the power supply line of the inner circuit is arranged below a first power supply line extending in a first direction; a second cell, in which a second switching element connecting first bias wiring connected to a first well region with first back-bias wiring, and plurality types of third switching elements connecting second bias wiring connected to a second well region with second back-bias wiring are arranged below a second power supply line extending in a second direction; and a third cell, in which a power switch controller for controlling the first switching element, fourth and fifth switching elements connecting the power voltage line corresponding to the first and second bias lines with the ground line, and a control circuit for controlling switching of the second and third switch elements are dispersed below a corner power supply line, connecting the first and second power supply lines. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译： 要解决的问题：提供一种提高设计效率的半导体集成电路器件，同时实现增强的功能。 解决方案：内部电路由第一电池围绕，其中连接电源线或接地线的第一开关元件与内部电路的电源线布置在第一电源线的下方，第一电源线延伸在第一电池 方向; 第二单元，其中连接到第一阱区的第一偏置布线与第一背偏置布线的第二开关元件以及连接到第二阱区的第二偏置布线与第二反偏置布线连接的多个第三开关元件 布置在沿第二方向延伸的第二电源线的下方; 以及第三单元，其中用于控制第一开关元件的电源开关控制器，将与第一和第二偏置线相对应的电力电压线与接地线连接的第四和第五开关元件，以及用于控制 第二和第三开关元件分散在角电源线下方，连接第一和第二电源线。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2009192461A
公开(公告)日：2009-08-27
申请号：JP2008035627
申请日：2008-02-18
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , H03K3/037
摘要： PROBLEM TO BE SOLVED: To reduce a delay overhead in a multiplexer-scanning flip-flop and make a layout area smaller.
SOLUTION: During normal operation, a selector 4a selects a data signal D, and a data-saving flip-flop 3 is in a holding state. During a scan path test, a scanning operation is performed by setting a standby signal Standby EN at a Lo level, and by setting the standby signal Standby EN at a Hi level, respectively. The data-saving flip-flop 3 always holds data obtained one cycle before, because data is transferred from the data-scanning flip-flop 3 to a multiplexer-scanning flip-flop 4. Thus, a buffer becomes unnecessary that is normally inserted in the scan path as measures to hold.
COPYRIGHT: (C)2009,JPO&INPIT摘要翻译： 要解决的问题：减少多路复用器扫描触发器中的延迟开销并使布局区域更小。 解决方案：在正常操作期间，选择器4a选择数据信号D，并且数据保存触发器3处于保持状态。 在扫描路径测试期间，通过将待机信号待机EN设置为低电平，并将待机信号待机EN分别设置为高电平来执行扫描操作。 由于数据从数据扫描触发器3传送到多路复用器扫描触发器4，所以数据保存触发器3总是保持一个周期获得的数据。因此，通常插入的缓冲器变得不必要 扫描路径作为保持的措施。 版权所有（C）2009，JPO＆INPIT
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