公开(公告)号：JP2009010264A

公开(公告)日：2009-01-15

申请号：JP2007171939

申请日：2007-06-29

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： H01L27/10 ,  H01L23/34 ,  H01L45/00 ,  H01L49/00

CPC分类号： G11C13/00 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008

摘要： PROBLEM TO BE SOLVED: To provide a resistive random access memory device and an integrated circuit device, which achieve high speed and low power consumption.
SOLUTION: The resistive random access memory device has: a memory chip using a resistive random access memory cell; and a heater which imparts a temperature bias for accelerating state change of the memory cell to the memory chip.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供实现高速度和低功耗的电阻式随机存取存储器件和集成电路器件。 解决方案：电阻随机存取存储器件具有：使用电阻随机存取存储单元的存储器芯片; 以及加热器，其向存储芯片施加用于加速存储单元的状态变化的温度偏差。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008258629A

公开(公告)日：2008-10-23

申请号：JP2008097482

申请日：2008-04-03

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： H01L21/822 ,  G01R31/28 ,  H01L21/82 ,  H01L27/04

CPC分类号： G01R31/3012 ,  G01R31/3004

摘要： PROBLEM TO BE SOLVED: To provide a system and method to identify regions where voltage supplied by the power distribution network of an IC chip is too low (or too high).
SOLUTION: Virtually uniform voltage is impressed on the power surface of the power distribution network connected to the IC chip. A plurality of current sources distributed over the chip are turned on. Voltage in a plurality of positions on the chip is sought. When the current source is turned on, a clock that works freely on a clock tree distributed over the chip becomes effective, and the operation of a function logic inside the IC is prohibited.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种识别由IC芯片的配电网络提供的电压太低（或太高）的区域的系统和方法。

解决方案：连接到IC芯片的配电网的功率表面上施加几乎均匀的电压。 分配在芯片上的多个电流源导通。 寻求芯片上多个位置的电压。 当电流源打开时，在芯片上分布的时钟树上自由工作的时钟变得有效，IC内部功能逻辑的操作被禁止。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006333489A

公开(公告)日：2006-12-07

申请号：JP2006145774

申请日：2006-05-25

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： H03L7/095

CPC分类号： H03L7/095 ,  H03L7/089 ,  H03L7/0895 ,  H03L2207/14 ,  Y10S331/02

摘要： PROBLEM TO BE SOLVED: To provide systems and methods for detecting phase-locked loop circuit lock, in particular, a lock detector configured to detect PLL stability for user-defined period of the time, prior to asserting of a PLL-lock-detected output. SOLUTION: Stability may be indicated by a counter, inserted into a PLL circuit and arranged between a phase-frequency detector and a charge pump. Because the counter value is acted on by the phase-frequency detector, PLL lock is indicated by counter value stability. The digital counter value can be provided to a digital charge pump and a lock detector simultaneously. The lock detector includes registers and difference detectors, to determine when the difference between counter values is below user-defined tolerance. The lock detector can include a variable timer to avoid false indications of lock, which may occur when counter values are sampled with the same frequency as a fluctuation frequency of the counter value. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：为了提供用于检测锁相环电路锁定的系统和方法，特别地，锁定检测器被配置为在断言PLL锁定之前检测用户定义的时间段的PLL稳定性 - 检测输出。

解决方案：稳定性可以由计数器指示，插入到PLL电路中并且布置在相位频率检测器和电荷泵之间。 由于计数器值由相位频率检测器作用，PLL锁定由计数器值稳定性指示。 数字计数器值可以同时提供给数字电荷泵和锁定检测器。 锁定检测器包括寄存器和差分检测器，以确定计数器值之间的差异何时低于用户定义的公差。 锁定检测器可以包括可变定时器，以避免错误的锁定指示，当计数器值以与计数器值的波动频率相同的频率被采样时可能发生。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2010092568A

公开(公告)日：2010-04-22

申请号：JP2008264319

申请日：2008-10-10

申请人： Toshiba Corp ,  株式会社東芝

发明人： HOSONO KOJI ,  TAKASE SATORU

IPC分类号： G11C13/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which effectively prevents memory cells from being erroneously set after a reset operation in a memory cell. SOLUTION: The semiconductor storage device includes a reset pulse-control circuit RSTCTL which applies a reset voltage Vreset to a selected bit line BL. The reset pulse-control circuit RSTCTL includes: a signal-output circuit SOUT which outputs a signal FLGRST on the basis of a current Ireset and a reference current Irefrst which each flow through a selected memory cell MC; and a current-holding circuit IMEM which holds a current which flows through the selected bit line or a wire electrically connected to a bit line for a predetermined time. The signal-output circuit SOUT determines the current Ireset on the basis of a current Ifwd+Ibld which is held by the current-holding circuit IMEM, and the reset pulse-control circuit RSTCTL stops the application of the reset voltage Vreset to the selected bit line BL on the basis of the signal FLGRST. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 解决的问题：提供一种有效地防止在存储器单元中的复位操作之后存储单元被错误地设置的半导体存储装置。 解决方案：半导体存储装置包括复位脉冲控制电路RSTCTL，其将复位电压Vreset施加到所选位线BL。 复位脉冲控制电路RSTCTL包括：信号输出电路SOUT，其输出基于电流Ireset的信号FLGRST和各自流过选择的存储单元MC的参考电流Irefrst; 以及保持流过选定位线的电流或电气连接到位线预定时间的电流的电流保持电路IMEM。 信号输出电路SOUT基于由电流保持电路IMEM保持的电流Ifwd + Ibld来确定电流Ireset，并且复位脉冲控制电路RSTCTL停止将复位电压Vreset施加到所选择的位 线BL基于信号FLGRST。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009141222A

公开(公告)日：2009-06-25

申请号：JP2007317642

申请日：2007-12-07

申请人： Toshiba Corp ,  株式会社東芝

发明人： HISADA TOSHIKI ,  WATANABE YOSHIHISA ,  ABE TAKUMI ,  TAKASE SATORU

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which increases margin reducing a random pattern, and secures withstanding voltage, even when microfabrication advances.
SOLUTION: The semiconductor integrated circuit device includes: a memory cell array 11; a sense circuit 12; a first hook up region F1 equipped with at least a first transfer transistor TF1-1 in which one end of a current path is connected to the sense circuit and another end is electrically connected to one first bit wire among a plurality of bit wires and a second transfer transistor TF1-2 in which one end of the current path is connected to the sense circuit and another end is electrically connected to one second bit wire among a plurality of bit wires; and a second hook up region F2 being arranged between the memory cell array and the first hook up region, equipped with at least a third transfer transistor TF2-1, in which one end of the current path is electrically connected to the first bit wire and another end is electrically connected to the one end of the current path of the first transfer transistor.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种半导体集成电路器件，即使在微细加工前进的情况下，也可以提高边缘，从而降低随机图案，并且确保耐受电压。 解决方案：半导体集成电路器件包括：存储单元阵列11; 感测电路12; 配备有至少第一传输晶体管TF1-1的第一连接区域F1，其中电流路径的一端连接到感测电路，另一端电连接到多个位线中的一个第一位线，以及 第二传输晶体管TF1-2，其中电流路径的一端连接到感测电路，另一端电连接到多个位线中的一个第二位线; 并且第二连接区域F2布置在存储单元阵列和第一挂接区域之间，配备有至少第三传输晶体管TF2-1，其中电流路径的一端电连接到第一位线，以及 另一端电连接到第一传输晶体管的电流路径的一端。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009099206A

公开(公告)日：2009-05-07

申请号：JP2007269973

申请日：2007-10-17

申请人： Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

发明人： MAEJIMA HIROSHI ,  ISOBE KATSUAKI ,  MUKAI HIDEO ,  TAKASE SATORU ,  INABA TSUNEO ,  FUKUDA YASUYUKI ,  TOKIWA NAOYA

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/105 ,  H01L45/00 ,  H01L49/00

CPC分类号： G11C13/0009 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2211/5642 ,  G11C2213/11 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72

摘要： PROBLEM TO BE SOLVED: To provide a resistance change memory device improved in data retention characteristics in storing multi-value data. SOLUTION: The resistance change memory device is constituted so that memory cells for storing rewritable resistance values in a nonvolatile state as data, and a high resistance side of the memory cell is in the stable state, and the multi-value data is stored, wherein at least three resistance values R0, R1 and R2 (R0 ΔR2 is satisfied. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种在存储多值数据时提高数据保持特性的电阻变化存储装置。 解决方案：电阻变化存储器件被构造成使得用于将非易失性状态的可重写电阻值存储为数据，并且存储单元的高电阻侧的存储单元处于稳定状态，并且多值数据为 存储，其中选择性地设置至少三个电阻值R0，R1和R2（R0 ΔR2的关系。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008034084A

公开(公告)日：2008-02-14

申请号：JP2007163231

申请日：2007-06-21

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： G11C11/401

CPC分类号： G11C7/1048 ,  G11C5/063 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093

摘要： PROBLEM TO BE SOLVED: To reduce the latency of data transfer between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. SOLUTION: The memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifier, a second-level sense amplifier, and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) top the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier). The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic. COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟。 解决方案：存储器系统使用具有一对第一级读出放大器，第二级读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。 每个读出放大器被配置为选择性地耦合到数据线。 在直接传送模式中，控制逻辑产生控制信号，该控制信号使得读出放大器将数据从第二级读出放大器（源读出放大器）的第一级传输到第二级读出放大器的顶端， 第一级第一级读出放大器（目标读出放大器）。 这些感测放大器的结构是传统的，并且通过改进的控制逻辑实现了系统的操作。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2013175252A

公开(公告)日：2013-09-05

申请号：JP2012038567

申请日：2012-02-24

申请人： Toshiba Corp ,  株式会社東芝

发明人： HIGASHI YUSUKE ,  TODA HARUKI ,  MUROOKA KENICHI ,  TAKASE SATORU ,  MITANI YUICHIRO ,  TORIYAMA SHUICHI

IPC分类号： G11C13/00 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  H01L45/00 ,  H01L49/00

CPC分类号： G11C7/00 ,  G11C7/04 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/22 ,  G11C2213/71 ,  G11C2213/72

摘要： PROBLEM TO BE SOLVED: To provide a countermeasure technique against heat that takes into account local temperature distribution at the time of actual operation.SOLUTION: A semiconductor memory comprises: a memory cell array that is provided with a plurality of blocks disposed in a matrix of n×m (where both of n and m are natural numbers equal to or more than 2) and allows respective ones of the plurality of blocks to independently perform operation of writing, reading or erasure; and a control section that performs a first cycle for performing the operation of writing, reading or erasure with respect to a first block out of the plurality of blocks and performs a second cycle for setting the inside of a range with a constant distance from the first block to a selection prohibition region, setting regions other than a selection region out of the plurality of blocks to a second block and performing the operation of writing, reading or erasure with respect to the second block until temperature relaxation time for relaxing a temperature in and around the first block increased by performing the first cycle elapses.

摘要翻译： 要解决的问题：提供一种在实际操作时考虑局部温度分布的针对热量的对策技术。解决方案：半导体存储器包括：存储单元阵列，其设置有以矩阵形式布置的多个块 n×m（其中n和m都是等于或大于2的自然数），并且允许多个块中的相应块独立地执行写入，读取或擦除的操作; 以及控制部，执行用于执行关于所述多个块中的第一块的写入，读取或擦除操作的第一周期，并且执行第二周期，用于设置与所述第一周期恒定距离的范围的内部 阻止到选择禁止区域，将多个块之外的选择区域以外的区域设置为第二块，并且执行关于第二块的写入，读取或擦除的操作，直到用于放宽温度的温度弛豫时间和 通过执行第一个循环过去，第一个块周围增加。

公开(公告)号：JP2009093724A

公开(公告)日：2009-04-30

申请号：JP2007261435

申请日：2007-10-05

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101

摘要： PROBLEM TO BE SOLVED: To provide a resistive random access memory device which allows simultaneous multi-bit writing. SOLUTION: The resistive random access memory device includes a cell array having a plurality of parallel word lines WL (WL1, WL2, ...), a plurality of bit lines BL (BL1, BL2, ...) intersecting with the word lines, and resistive random access memory cells disposed on intersection parts of the word lines and the bit lines and allowing reversible setting of resistance; a word line driving circuit which provides a selective driving voltage to a selected word line selected from among the plurality of word lines of the cell array; and a bit line driving circuit which drives the plurality of bit lines so as to simultaneously set both a set mode where a transition from a first resistance state to a second resistance state is caused and a reset mode where a transition from the second resistance state to the first resistance state on the memory cells selected by the selected word line. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供允许同时进行多位写入的电阻随机存取存储器件。 电阻式随机存取存储器件包括具有多个并行字线WL（WL1，WL2，...）的单元阵列，与 字线和设置在字线和位线的交叉部分上的电阻随机存取存储单元，并允许电阻的可逆设置; 字线驱动电路，其向从所述单元阵列的所述多个字线中选择的选定字线提供选择性驱动电压; 以及位线驱动电路，其驱动多个位线，以便同时设定从第一电阻状态到第二电阻状态的转变的设定模式和从第二电阻状态到第二电阻状态的转变的复位模式 由所选字线选择的存储器单元上的第一电阻状态。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008227500A

公开(公告)日：2008-09-25

申请号：JP2008060259

申请日：2008-03-10

申请人： Toshiba Corp ,  株式会社東芝

发明人： TAKASE SATORU

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： PROBLEM TO BE SOLVED: To provide a system and a method for increasing a voltage to be supplied in a predetermined region in an integrated circuit.
SOLUTION: The system includes an integrated circuit chip. A power source supply network is connected to the integrated circuit chip and includes a plurality of metal wire layers and a plurality of via layers. An electric power plane is connected to the power source supply network and divided into two or more portions individually connected to distinct power source supply networks. The power source is connected to a portion of the electric power plane and configured so as to apply a first voltage to a first portion of the portion and also apply a second voltage, different from the first voltage, to a second portion of the portion. The first and second voltages are selected so as to generate a substantially uniform voltage across the integrated circuit chip. The metal wire layers are arranged alternately with the vias. The electric power supply network further includes a contact layer that connects the uppermost metal layer of the metal layers to the electric power plane.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：提供一种用于增加在集成电路中的预定区域中提供的电压的系统和方法。

解决方案：该系统包括一个集成电路芯片。 电源供应网络连接到集成电路芯片，并且包括多个金属线层和多个通孔层。 电力平面连接到电源供应网络，并被划分成独立地连接到不同电源供应网络的两个或多个部分。 电源连接到电力平面的一部分并且被配置为向该部分的第一部分施加第一电压，并且将不同于第一电压的第二电压施加到该部分的第二部分。 选择第一和第二电压以便在集成电路芯片上产生基本均匀的电压。 金属线层与通孔交替排列。 电力供给网络还包括将金属层的最上层金属层与电力平面连接的接触层。 版权所有（C）2008，JPO＆INPIT