公开(公告)号：US5230001A

公开(公告)日：1993-07-20

申请号：US666538

申请日：1991-03-08

申请人： Susheel J. Chandra ,  Tushar Gheewala

发明人： Susheel J. Chandra ,  Tushar Gheewala

IPC分类号： G01R31/3183

CPC分类号： G01R31/318371 ,  G01R31/318392

摘要： During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To test for a select fault condition, the sequential circuit needs to be in a desired state. While in such desired state, a test vector is applied and select internal circuit element responses are monitored. If the desired state occurs during a sequence of design verification patterns, then the test vector is applied between successive patterns before the IC clock has a transition. By applying the test signal, monitoring the response, then reapplying the design verification pattern before the clock changes, the IC subsequent state which would occur had the test vector been omitted still occurs. If a desired state does not occur during the sequence of design verification patterns, then a select state similar to the desired state is identified. When such select state occurs, control signals are applied through internal test points to force a state change to the desired state. Thereafter, the appropriate test vector is applied and the response is monitored to check the fault condition. All such steps occur before a clock transition so that the state and design verification pattern occurring at the beginning of the clock cycle, also occur before the next transition to the clock cycle. Accordingly, the design verification pattern sequence is not invalidated.

摘要翻译： 在顺序电路IC的主输入引脚应用一系列设计验证模式期间，测试矢量在模式之间进行拼接以测试故障状况。 随着设计验证模式的顺序应用，顺序电路的状态发生变化。 为了测试选择故障条件，顺序电路需要处于所需状态。 在这样的期望状态下，应用测试矢量并监视内部电路元件响应。 如果在设计验证模式序列期间发生所需状态，则在IC时钟转换之前，在连续模式之间应用测试矢量。 通过应用测试信号，监视响应，然后在时钟变化之前重新应用设计验证模式，如果测试向量被忽略，则发生的IC后续状态仍然发生。 如果在设计验证模式的序列期间没有发生期望的状态，则识别与期望状态相似的选择状态。 当这种选择状态发生时，通过内部测试点施加控制信号以迫使状态改变到所需状态。 此后，应用适当的测试向量并监视响应以检查故障状况。 所有这些步骤都发生在时钟转换之前，使得在时钟周期开始时发生的状态和设计验证模式也发生在下一次到时钟周期的转换之前。 因此，设计验证模式序列不会失效。

公开(公告)号：US4937826A

公开(公告)日：1990-06-26

申请号：US242848

申请日：1988-09-09

申请人： Tushar R. Gheewala ,  Robert J. Lipp

发明人： Tushar R. Gheewala ,  Robert J. Lipp

IPC分类号： G01R31/26 ,  G01R31/30 ,  G01R31/316 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66

CPC分类号： G01R31/316 ,  G01R31/30 ,  G01R31/318516

摘要： An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults. A method according to the invention includes path sensitization whereby test patterns can be reduced to Boolean expressions.

摘要翻译： 用于测试集成电路中的故障的装置附接到感测线，感测线耦合到集成电路内的测试结构的逻辑门的输出节点，例如内置于集成电路装置中的“交叉检验”测试结构。 相关方法在使用感测线在感测测试点处的信号电平之前，将感测线预充电到已知的信号电平。 与传感线连接的读出放大器或比较器的设备可以同步调整比较器的检测电平，以测试输出“一”最小电平（VOH）或输出“零”最大电平（VOL），以测试其他类 的故障。 附接到感测线的装置可以在测试序列中的预选时间将电荷注入逻辑门的输出节点，以修改该输出节点处的信号电平以测试故障。 根据本发明的方法包括路径敏化，其中测试图案可以减少到布尔表达式。

公开(公告)号：US5495486A

公开(公告)日：1996-02-27

申请号：US929873

申请日：1992-08-11

申请人： Tushar Gheewala

发明人： Tushar Gheewala

IPC分类号： G01R31/3185 ,  H04B17/00 ,  G11C29/00

CPC分类号： G01R31/3185

摘要： Individual elements of an integrated circuit such as storage elements, (for example, latch elements), can be selectively coupled to select lines and probe lines. During normal operation the latches are not connected to the select lines and behave as a normal latch. During a write/control test operation, the latch is connected to a select line and data placed on the select line is provided to an input of latch. Thereafter, the latch is placed into a latching state in response to the probe line and the clock signal, latching the data provided from the select line into latch. In order to read/observe data, the clock line and probe line are controlled to route data onto the associated select line. In one embodiment the probe line controls a transistor switch that connects the select line to the input of the latch. The probe line also controls a transmission gate which is placed in the latch to toggle the latch between a latching condition and a non-latching condition, in response to signals on the probe line. Preferably each select line and probe line are attached to a plurality of elements and each element is connected to one select line and one probe line. Thus, by placing signals on the select line and probe line, any individual IC element can be addressed for controlling and/or observing.

摘要翻译： 诸如存储元件（例如，锁存元件）的集成电路的各个元件可以选择性地耦合到选择线和探针线。 在正常操作期间，锁存器不连接到选择线并表现为正常锁存器。 在写入/控制测试操作期间，锁存器连接到选择线，并且放置在选择线上的数据被提供给锁存器的输入。 此后，响应于探测线和时钟信号，锁存器被置于锁存状态，将从选择线提供的数据锁存到锁存器中。 为了读取/观察数据，时钟线和探针线被控制以将数据路由到相关的选择线上。 在一个实施例中，探针线控制将选择线连接到锁存器的输入端的晶体管开关。 探针线还控制放置在闩锁中的传输门，以响应于探针线上的信号而在锁存状态和非锁定状态之间切换闩锁。 优选地，每个选择线和探针线连接到多个元件，并且每个元件连接到一个选择线和一个探针线。 因此，通过在选择线和探针线上放置信号，可以寻址任何单独的IC元件以进行控制和/或观察。

公开(公告)号：US5471152A

公开(公告)日：1995-11-28

申请号：US133588

申请日：1993-10-08

申请人： Tushar Gheewala ,  Rustam Mehta ,  Prab Varma

发明人： Tushar Gheewala ,  Rustam Mehta ,  Prab Varma

IPC分类号： G01R31/30 ,  G01R31/3185 ,  G01R31/00 ,  G01R31/02

CPC分类号： G01R31/3016 ,  G01R31/3185

摘要： A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC's sense lines. The third switch is controlled by one of the IC's probe lines. A second sense input loads a second logic state into the slave latch through a fourth switch, the second sense input being coupled to another one of the IC's sense lines. The fourth switch is controlled by a second control signal. The second logic state replaces the first logic state in the slave latch upon application of the clock signal. The desired signal transition is generated where the first logic state is different from the second logic state.

摘要翻译： 描述用于测试集成电路中的延迟路径的存储元件。 存储元件可以用于具有探针和感测线的矩阵的集成电路中。 存储元件在延迟路径的输入上产生逻辑转换，逻辑转换与时钟信号紧密同步。 存储元件包括数据输入和耦合到延迟路径的输入的数据输出。 主锁存器通过第一开关从数据输入端接收数据，第一开关由时钟信号的补码控制。 从锁存器通过第二开关从主锁存器接收数据，第二开关由时钟信号的真实来控制。 第一感测输入通过第三开关将第一逻辑状态加载到主锁存器中，第一感测输入耦合到IC的感测线之一。 第三个开关由IC的探针线之一控制。 第二感测输入通过第四开关将第二逻辑状态加载到从锁存器中，第二感测输入耦合到IC的感测线中的另一个。 第四开关由第二控制信号控制。 第二逻辑状态在施加时钟信号时替代从锁存器中的第一逻辑状态。 产生期望的信号转换，其中第一逻辑状态不同于第二逻辑状态。

公开(公告)号：US5436801A

公开(公告)日：1995-07-25

申请号：US120148

申请日：1993-09-09

申请人： Tushar Gheewala ,  Rustam Mehta ,  Timothy Saxe

发明人： Tushar Gheewala ,  Rustam Mehta ,  Timothy Saxe

IPC分类号： H01L23/528 ,  H01R9/00

CPC分类号： H01L23/5286 ,  H01L2924/0002

摘要： An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae. Contacts to the first metal level are used as a means by which the power antennae are connected to the circuit elements. Vias to the metal levels overlying the first metal level are used as a means by which the power carrying tracks are connected to the power bridges and the power antennae, and by which the power bridges are connected to other power bridges and the power antennae.

摘要翻译： 一种集成电路结构，其采用覆盖电路元件阵列的至少两个金属电平。 每个金属层包含可用于供电和互连电路元件的信号路由资源。 金属水平包括直接覆盖电路元件阵列的第一金属水平，中间金属水平（如果存在多于两个金属水平）以及覆盖所有其它金属水平的顶部金属水平。 电力承载轨道设置在顶部金属水平面上。 功率天线设置在第一金属级，但仅在必要时向电路元件供电。 功率天线用于将电力承载轨道连接到电路元件。 功率桥被布置在第一金属层与顶层金属层之间的中间金属层。 电源桥用于将电力传输轨道连接到电源天线。 与第一金属电平的接触被用作电力天线连接到电路元件的手段。 使用覆盖在第一金属层上的金属层的通路用作电力承载轨道连接到电力桥和功率天线的装置，并且电力桥连接到其它电力桥和功率天线。

公开(公告)号：US5206862A

公开(公告)日：1993-04-27

申请号：US667611

申请日：1991-03-08

申请人： Susheel J. Chandra ,  Tushar Gheewala

发明人： Susheel J. Chandra ,  Tushar Gheewala

IPC分类号： G01R31/28

CPC分类号： G01R31/2844

摘要： An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed. Control signals are produced from the data register contents. The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points. According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents. A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals. Predesigned test sequences enable fast continuous testing of the IC.

摘要翻译： IC具有本地测试电路，包括测试点阵列，指令寄存器，数据寄存器，探针线驱动器和控制/感测线驱动器/接收器。 为了测试IC，加载指令寄存器启动测试电路以寻址选择的测试点以接收控制信号，并寻址要检测响应信号的其他选择测试点。 控制信号由数据寄存器内容产生。 数据寄存器内容是根据数据寄存器的先前内容和由选择的测试点的响应信号形成的位模式导出的。 根据一个实施例，先前内容被专门用于响应信号的位模式以导出新的数据寄存器内容。 通过使用专门对数据寄存器内容进行OR运算的先前响应信号来执行连续测试，以产生后续控制信号。 预先设计的测试序列可以快速连续测试IC。

公开(公告)号：US5179534A

公开(公告)日：1993-01-12

申请号：US601969

申请日：1990-10-23

申请人： Kerry M. Pierce ,  Thomas V. Ferry

发明人： Kerry M. Pierce ,  Thomas V. Ferry

IPC分类号： G11C11/413 ,  G11C11/41 ,  G11C29/00 ,  G11C29/04 ,  G11C29/56 ,  H03K3/356

CPC分类号： H03K3/356086 ,  G11C11/41 ,  G11C29/04

摘要： An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.

摘要翻译： 具有包括相交探测线和控制/感测线的测试网格结构的IC被用于将期望的逻辑状态直接应用于选择的存储元件的内部传输路径。 开关位于每个十字路口处，以将期望的逻辑状态传送到内部传输路径。 为了实现所需逻辑状态的重写和存储，常规存储元件被修改为包括由覆盖使能信号激活的传输门。 覆盖使能信号由一个或多个探测线定义。 为了覆盖存储元件的内容，通过用耦合到这种开关的探针线接通开关来选择存储元件，同时通过接收覆盖使能信号来禁止包含的传输门。 控制/感测线的逻辑状态被传导到存储元件到所包含的传输门，其中它覆盖当前内容并被存储。

公开(公告)号：US5157627A

公开(公告)日：1992-10-20

申请号：US554313

申请日：1990-07-17

申请人： Tushar R. Gheewala

发明人： Tushar R. Gheewala

IPC分类号： G01R31/3185 ,  G11C7/20 ,  G11C29/08

CPC分类号： G01R31/3185 ,  G11C29/08 ,  G11C7/20

摘要： A desired signal level is set at select storage elements of an integrated circuit without relying on signals applied to the primary input pins of the integrated circuit. Instead, a signal is applied through a test matrix to the input, output or internal line of a select storage element. With the drive of the applied signal being greater than the drive of the signals occurring at the select storage element of the integrated circuit, the applied signal level magnitude is forced upon the storage element. Once the drive of the applied signal is reduced relative to the drive of the storage element signals so as to be less than or equal to the drive of the storage element signals, the output level of the select storage element remains at the desired level. According to one embodiment, the power supply of the test electronics which generates the applied signal is of greater magnitude than the integrated circuit power supply at power up during the state-setting operation to achieve the greater relative drive. During a state-observing operation, the power supply voltage of the test electronics is approximately equal to the power supply voltage of the integrated circuit so as not to inadvertently change the output state of the select storage element.

摘要翻译： 在集成电路的选择存储元件处设置期望的信号电平，而不依赖于施加到集成电路的主输入引脚的信号。 相反，通过测试矩阵将信号施加到选择存储元件的输入，输出或内部行。 随着施加信号的驱动大于在集成电路的选择存储元件处发生的信号的驱动，施加的信号电平幅度被强制在存储元件上。 一旦所施加的信号的驱动相对于存储元件信号的驱动减小以便小于或等于存储元件信号的驱动，则选择存储元件的输出电平保持在期望的水平。 根据一个实施例，产生施加的信号的测试电子器件的电源在状态设置操作期间在加电时的集成电路电源具有更大的幅度，以实现更大的相对驱动。 在状态观察操作期间，测试电子器件的电源电压近似等于集成电路的电源电压，以免不经意地改变选择存储元件的输出状态。

公开(公告)号：US4975640A

公开(公告)日：1990-12-04

申请号：US482458

申请日：1990-02-20

申请人： Robert J. Lipp

发明人： Robert J. Lipp

IPC分类号： G06F11/27 ,  G11C19/00 ,  G11C19/38

CPC分类号： G11C19/38 ,  G06F11/27 ,  G11C19/00

摘要： A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.