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公开(公告)号：US08456210B2
公开(公告)日：2013-06-04
申请号：US12961523
申请日：2010-12-07
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0891
摘要： A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.
摘要翻译： 校准延迟锁定环（DLL）以获得DLL中偏移误差的度量。 偏移误差在正常运行中得到补偿。 在一个实施例中，与偏移测量相对应的电流被强制为携带表示参考信号和反馈信号之间的相位失配的误差信号的一对路径之一。 在另一个实施例中，对应于偏移量的附加延迟被引入到一对路径之一上。 因此，在DLL的正常操作中，偏移误差被大大地消除。 DLL采用放大器代替电荷泵，以消除由于电荷泵引起的系统偏移误差。 设计DLL中的相位检测器，使得相位检测器的误差输出的重叠间隔至少为参考信号的周期的一半，从而借助于高频操作。
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2.发明申请SIGMA DELTA DIGITAL TO ANALOG CONVERTER WITH WIDE OUTPUT RANGE AND IMPROVED LINEARITY 有权SIGMA DELTA数字到具有宽输出范围和改进线性度的模拟转换器公开(公告)号：US20100066455A1
公开(公告)日：2010-03-18
申请号：US12211834
申请日：2008-09-17
CPC分类号： H03L7/093 , H03M1/68 , H03M1/747 , H03M3/502 , H03M7/3004
摘要： A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator.
摘要翻译： 使用单个DAC产生第一模拟量部分和第二模拟量部分的Σ-ΔDAC具有分别与接收数字值的最高有效位（MSB）和最低有效位（LSB）成比例的强度。 添加两个部分以产生表示数字值的强度的模拟输出。 在一个实施例中，单个DAC包含一组电流源，其中一些电流源（由MSB的值确定）被连接以在第一路径上提供对应的输出电流。 由LSB的值确定的一些其他电流源被控制为连接以在第二路径上提供相应的输出电流。 电流连接到第二路径的持续时间由Σ-Δ调制器的输出决定。
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3.发明授权Generating an output signal with a frequency that is a non-integer fraction of an input signal 有权以输入信号的非整数分数的频率生成输出信号公开(公告)号：US07560962B2
公开(公告)日：2009-07-14
申请号：US11609347
申请日：2006-12-12
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
IPC分类号： H03L7/06
CPC分类号： H03K23/48 , H03L7/0812 , H03L7/16
摘要： Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.
摘要翻译： 产生具有输入信号频率的1 /（M + F）频率的输出信号，其中M表示整数，F表示非零分数。 假设在一个实施例中，F等于（Q / R），其中Q和R是整数，产生在输入信号的一个时钟周期内相移相等程度（相对于最接近的相移的）中间信号。 选择电路可以在一个时钟周期中选择一个中间信号，在Q个时钟周期中选择具有增加的相移的连续信号，并且使剩余的M中的与上一个时钟周期相同的移位的中间信号 时钟周期。 计数器对选择电路的输出中的状态变化进行计数，并且在计数器计数M的时间点产生表示输出信号的边沿的脉冲。
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公开(公告)号：US20090058480A1
公开(公告)日：2009-03-05
申请号：US11848241
申请日：2007-08-31
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
CPC分类号： H03K19/0005 , H03K19/00361 , H04L25/0276 , H04L25/0278 , H04L25/0282 , H04L25/0288 , H04L25/12
摘要： A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.
摘要翻译： 与传输焊盘系统电路交互的串行接口，其中跨越系统电压源计算差分阻抗，包括用于控制发射机上升 - 下降转换（选择性地加速或减慢转换）的方案，而不需要额外的时序控制或影响反射 发射机端口系数。 该方案使用至少一个预充电电容器，例如PMOS电容器，与发射器焊盘相互作用，并通过电阻或其它方式通过差分阻抗与开关连接。 修改的方案使用可以是NMOS开关的开关来连接与传输焊盘连接的第一和第二平行连接的PMOS电容器。 该方案可以用在例如MIPI D-PHY兼容的DSI发射机中。 800 Mbps，低信号共模。 该方案控制包括发射机在内的高速电路的信号转换时间，并使用已经可用于电路的DATA信号。
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公开(公告)号：US08411804B2
公开(公告)日：2013-04-02
申请号：US13031257
申请日：2011-02-21
CPC分类号： H04L25/4902
摘要： A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.
摘要翻译： 数字PWM解调器包括第一组延迟单元，用于接收PWM信号并且沿正向方向传播PWM信号第一间隔。 在第一间隔结束时获得的延迟信号通过延迟单元反向传播第二间隔。 逻辑零在第二个间隔开始时馈送到最后一个单元格。 在第二间隔结束时，延迟单元中的最后一个单元的输出表示在PWM信号上调制的数据值。 数字PWM解调器包括被设计为与第一组延迟单元相同的第二组延迟单元。 第一组延迟单元和第二组延迟单元结合附加数字电路解调PWM信号的交替周期。
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6.发明申请Generating an Output Signal With a Frequency That is a Non-Integer Fraction of an Input Signal 有权以输入信号的非整数分数的频率生成输出信号公开(公告)号：US20080136471A1
公开(公告)日：2008-06-12
申请号：US11609347
申请日：2006-12-12
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
CPC分类号： H03K23/48 , H03L7/0812 , H03L7/16
摘要： Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.
摘要翻译： 产生具有输入信号频率的1 /（M + F）频率的输出信号，其中M表示整数，F表示非零分数。 假设在一个实施例中，F等于（Q / R），其中Q和R是整数，产生在输入信号的一个时钟周期内相移相等程度（相对于最接近的相移的）中间信号。 选择电路可以在一个时钟周期中选择一个中间信号，在Q个时钟周期中选择具有增加的相移的连续信号，并且使剩余的M中的与上一个时钟周期相同的移位的中间信号 时钟周期。 计数器对选择电路的输出中的状态变化进行计数，并且在计数器计数M的时间点产生表示输出信号的边沿的脉冲。
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公开(公告)号：US20120213314A1
公开(公告)日：2012-08-23
申请号：US13031257
申请日：2011-02-21
IPC分类号： H04L27/06
CPC分类号： H04L25/4902
摘要： A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.
摘要翻译： 数字PWM解调器包括第一组延迟单元，用于接收PWM信号并且沿正向方向传播PWM信号第一间隔。 在第一间隔结束时获得的延迟信号通过延迟单元反向传播第二间隔。 逻辑零在第二个间隔开始时馈送到最后一个单元格。 在第二间隔结束时，延迟单元中的最后一个单元的输出表示在PWM信号上调制的数据值。 数字PWM解调器包括被设计为与第一组延迟单元相同的第二组延迟单元。 第一组延迟单元和第二组延迟单元结合附加数字电路解调PWM信号的交替周期。
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公开(公告)号：US20120139595A1
公开(公告)日：2012-06-07
申请号：US12961523
申请日：2010-12-07
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0891
摘要： A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.
摘要翻译： 校准延迟锁定环（DLL）以获得DLL中偏移误差的度量。 偏移误差在正常运行中得到补偿。 在一个实施例中，与偏移测量相对应的电流被强制为携带表示参考信号和反馈信号之间的相位失配的误差信号的一对路径之一。 在另一个实施例中，对应于偏移量的附加延迟被引入到一对路径之一上。 因此，在DLL的正常操作中，偏移误差被大大地消除。 DLL采用放大器代替电荷泵，以消除由于电荷泵引起的系统偏移误差。 设计DLL中的相位检测器，使得相位检测器的误差输出的重叠间隔至少为参考信号的周期的一半，从而借助于高频操作。
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公开(公告)号：US07737747B2
公开(公告)日：2010-06-15
申请号：US11848241
申请日：2007-08-31
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
IPC分类号： H03K5/12
CPC分类号： H03K19/0005 , H03K19/00361 , H04L25/0276 , H04L25/0278 , H04L25/0282 , H04L25/0288 , H04L25/12
摘要： A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.
摘要翻译： 与传输焊盘系统电路交互的串行接口，其中跨越系统电压源计算差分阻抗，包括用于控制发射机上升 - 下降转换（选择性地加速或减慢转换）的方案，而不需要额外的时序控制或影响反射 发射机端口系数。 该方案使用至少一个预充电电容器，例如PMOS电容器，与发射器焊盘相互作用，并通过电阻或其它方式通过差分阻抗与开关连接。 修改的方案使用可以是NMOS开关的开关来连接与传输焊盘连接的第一和第二平行连接的PMOS电容器。 该方案可以用在例如MIPI D-PHY兼容的DSI发射机中。 800 Mbps，低信号共模。 该方案控制包括发射机在内的高速电路的信号转换时间，并使用已经可用于电路的DATA信号。
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公开(公告)号：US07429895B2
公开(公告)日：2008-09-30
申请号：US11366006
申请日：2006-02-28
申请人： Prakash Easwaran , Anant Shankar Kamath , Rupak Ghayal , Birman Chattopadhyay , Gopal Krishna Nayak , Sameer Raghavendra Joshi , Mithun Guddethota Neelakant , Subhash Yekanath Pai , Shivaprakash Halagur
发明人： Prakash Easwaran , Anant Shankar Kamath , Rupak Ghayal , Birman Chattopadhyay , Gopal Krishna Nayak , Sameer Raghavendra Joshi , Mithun Guddethota Neelakant , Subhash Yekanath Pai , Shivaprakash Halagur
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , E05Y2400/30 , H03L7/099 , H03L7/189
摘要： Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.
摘要翻译： 公开了用于漂移补偿的各种系统和方法。 作为一个示例，公开了一种用于补偿控制电路中的漂移的系统，其包括至少两个控制信号。 控制信号之一由容易漂移的电路提供。 该控制信号被提供给被控制的系统或设备，以及检测电路。 检测电路可操作以检测控制信号中的漂移。 此外，检测电路提供另一控制信号，该控制信号根据所接收的控制信号中的漂移而变化。
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