公开(公告)号：US5126822A

公开(公告)日：1992-06-30

申请号：US739625

申请日：1991-08-02

申请人： Roelof H. W. Salters ,  Betty Prince

发明人： Roelof H. W. Salters ,  Betty Prince

IPC分类号： H01L23/495 ,  H01L23/50 ,  H01L23/64

CPC分类号： B82Y10/00 ,  H01L23/49589 ,  H01L23/50 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011

摘要： An IC is provided with supply pins extending beyond the chip's encapsulation. The location of the supply pins is chosen so as to minimize the length of the associated bonding wires. Moreover the supply pins are located next to each other so as to reduce the effective inductance of the associated bonding wires. Output pins connected with on-chip buffers are located next to the supply pins so as to reduce the length of the buffer's supply lines, giving rise to a further reduction is inductive parasitic effects.

摘要翻译： IC提供了超出芯片封装的电源引脚。 选择供应销的位置以使相关联的接合线的长度最小化。 此外，电源引脚彼此相邻，以便减少相关联的接合线的有效电感。 与片上缓冲器连接的输出引脚位于电源引脚旁边，以减少缓冲器电源线的长度，从而进一步降低电感性寄生效应。

公开(公告)号：US6000027A

公开(公告)日：1999-12-07

申请号：US934982

申请日：1992-08-25

申请人： Basavaraj I. Pawate ,  Betty Prince

发明人： Basavaraj I. Pawate ,  Betty Prince

IPC分类号： G06F12/00 ,  G06F15/78 ,  G06T1/60 ,  G09G5/39 ,  G06F15/00

CPC分类号： G09G5/39 ,  G09G2360/12

摘要： A smart video memory (10) is provided that includes data storage (12 and 18), a serial access memory (19), and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard video memory device.

摘要翻译： 提供了一种智能视频存储器（10），其包括用于执行存储在数据存储区域（12和18）中的指令的数据存储器（12和18），串行存取存储器（19）和处理核心（14和16） 。 在外部，智能存储器（10）可以作为标准视频存储器件直接访问。

公开(公告)号：US4951254A

公开(公告)日：1990-08-21

申请号：US272180

申请日：1988-11-16

申请人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

发明人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/00 ,  G06F11/22 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46

CPC分类号： G06F11/2273 ,  G01R31/31701 ,  G06F11/006 ,  G11C29/46

摘要： Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

摘要翻译： 具有多个测试模式的随机存取存储器单元，其被构造为集成电路，并且不包括特定的输入/输出引脚来定义和命令通过测试模式。 该单元配备有用于检测在通常使用的一组序列内但是其电压是否包括在指定的电压范围内的未包含的预定义逻辑信号序列的装置（1） 对于这样的信号，被提供给某些输入（CE，WE，AO），并且当检测到这样的序列时，将单元置于测试模式。 为了定义要执行的测试的性质，单元的地址输入端（A1-A8）连接到测试模式解码电路（2），其中将施加到所述输入端的数据用作 定义要执行的测试的性质的数据。