公开(公告)号：US4951254A

公开(公告)日：1990-08-21

申请号：US272180

申请日：1988-11-16

申请人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

发明人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/00 ,  G06F11/22 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46

CPC分类号： G06F11/2273 ,  G01R31/31701 ,  G06F11/006 ,  G11C29/46

摘要： Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

摘要翻译： 具有多个测试模式的随机存取存储器单元，其被构造为集成电路，并且不包括特定的输入/输出引脚来定义和命令通过测试模式。 该单元配备有用于检测在通常使用的一组序列内但是其电压是否包括在指定的电压范围内的未包含的预定义逻辑信号序列的装置（1） 对于这样的信号，被提供给某些输入（CE，WE，AO），并且当检测到这样的序列时，将单元置于测试模式。 为了定义要执行的测试的性质，单元的地址输入端（A1-A8）连接到测试模式解码电路（2），其中将施加到所述输入端的数据用作 定义要执行的测试的性质的数据。

公开(公告)号：US5265064A

公开(公告)日：1993-11-23

申请号：US449666

申请日：1989-12-12

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/41 ,  H03K3/033 ,  H03K3/78 ,  H03K5/04 ,  H03K5/156 ,  G11C8/00

CPC分类号： H03K5/04 ,  H03K3/033 ,  H03K5/156

摘要： A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3). The circuit may be used as an equalisation pulse generator for a data path in a semiconductor memory integrated circuit.

公开(公告)号：US5224071A

公开(公告)日：1993-06-29

申请号：US390326

申请日：1989-08-07

申请人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C11/41 ,  G11C8/06

CPC分类号： G11C8/06

摘要： An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

摘要翻译： 可寻址存储器单元具有地址输入缓冲器电路，其输出一对输出连接，在读出或写入模式中，存在彼此互补的两个信号，但是也可以以这样的方式采用相等的值， 预解码器和线选择器来选择所有或没有选择线来控制所访问的存储器的单元。

公开(公告)号：US5212413A

公开(公告)日：1993-05-18

申请号：US726470

申请日：1991-07-08

申请人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

发明人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

IPC分类号： H03K19/173 ,  G11C29/04 ,  H03K3/356

CPC分类号： H03K3/356008

摘要： When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

公开(公告)号：US4929911A

公开(公告)日：1990-05-29

申请号：US296462

申请日：1989-05-22

申请人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： H03K19/0185 ,  H03K17/687 ,  H03K19/003

CPC分类号： H03K19/00315

摘要： A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

公开(公告)号：US5087840A

公开(公告)日：1992-02-11

申请号：US657334

申请日：1991-02-13

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, decease ,  by Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, decease ,  by Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/413 ,  G11C7/10 ,  H03K19/0948

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106

摘要： An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

公开(公告)号：US5033024A

公开(公告)日：1991-07-16

申请号：US453637

申请日：1989-12-20

申请人： Cormac M. O'Connell ,  Leonardus Pfennings, deceased ,  by Henricus J. Kunnen, executor ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Cormac M. O'Connell ,  Leonardus Pfennings, deceased ,  by Henricus J. Kunnen, executor ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/846

摘要： An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

公开(公告)号：US4931667A

公开(公告)日：1990-06-05

申请号：US266172

申请日：1988-11-02

申请人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

发明人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

IPC分类号： G06F3/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/41 ,  G11C11/419

CPC分类号： G11C7/1048

摘要： Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

摘要翻译： 通过由差分放大器评估的差分信号经由双总线传输数据，特别是出于防止干扰的原因。 然而，这种差分放大器仅具有有限的输入电压范围，或其中不能操作的输入信号的死电压范围。 为了防止两条总线上的电压进入该死区，由于总线上的共模干扰信号或由于差分放大器的馈电电压的电压下降，两条总线被连接 根据本发明，调整电路使得两个总线的电压在死电压范围之外的方向上改变相同的量。 这可以防止差分放大器的未指定条件，而不会明显影响两条总线上的差分信号。 描述了集成存储器的应用。

公开(公告)号：US5040152A

公开(公告)日：1991-08-13

申请号：US265640

申请日：1988-11-01

申请人： Peter H. Voss ,  Leonardus C. M. G. Pfennings ,  Cormac M. O'Connell ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Peter H. Voss ,  Leonardus C. M. G. Pfennings ,  Cormac M. O'Connell ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C8/12 ,  G11C11/401 ,  G11C11/408 ,  H01L27/10

CPC分类号： G11C5/025 ,  G11C8/12

摘要： A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

摘要翻译： 静态RAM存储器针对速度进行了优化。 存储器分为主存储矩阵，每个主存储矩阵分为存储块。 存储器块被分组，每组具有共同的地址位，然而每个组耦合到单独的焊盘或焊盘组。 这些焊盘在封装上互连到公共封装引脚。

公开(公告)号：US06359316B1

公开(公告)日：2002-03-19

申请号：US08933562

申请日：1997-09-19

申请人： Peter H. Voss ,  Andrew Walker ,  Jeff Watt ,  Ashish Pancholy ,  Cathal G. Phelan ,  Patrick Zicolello ,  Christopher J. Petti

发明人： Peter H. Voss ,  Andrew Walker ,  Jeff Watt ,  Ashish Pancholy ,  Cathal G. Phelan ,  Patrick Zicolello ,  Christopher J. Petti

IPC分类号： H01L2976

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

摘要翻译： 具有一个或多个闭锁抑制扩散区域的半导体（优选CMOS）器件。 闩锁抑制区域与互补P沟道和N沟道晶体管相邻，并且通常用于抑制或防止闩锁，而不增加器件的管芯尺寸。