公开(公告)号：US4951254A

公开(公告)日：1990-08-21

申请号：US272180

申请日：1988-11-16

申请人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

发明人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/00 ,  G06F11/22 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46

CPC分类号： G06F11/2273 ,  G01R31/31701 ,  G06F11/006 ,  G11C29/46

摘要： Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

摘要翻译： 具有多个测试模式的随机存取存储器单元，其被构造为集成电路，并且不包括特定的输入/输出引脚来定义和命令通过测试模式。 该单元配备有用于检测在通常使用的一组序列内但是其电压是否包括在指定的电压范围内的未包含的预定义逻辑信号序列的装置（1） 对于这样的信号，被提供给某些输入（CE，WE，AO），并且当检测到这样的序列时，将单元置于测试模式。 为了定义要执行的测试的性质，单元的地址输入端（A1-A8）连接到测试模式解码电路（2），其中将施加到所述输入端的数据用作 定义要执行的测试的性质的数据。

公开(公告)号：US20050254315A1

公开(公告)日：2005-11-17

申请号：US10525662

申请日：2003-07-31

申请人： Roelof Salters

发明人： Roelof Salters

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/419 ,  G11C15/00 ,  G11C15/04 ,  G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/12 ,  G11C8/12 ,  G11C11/419 ,  G11C15/00 ,  G11C15/04

摘要： A word line driver circuit (10) is coupled to word lines (18) of a memory matrix, for example a matrix of content addressable cells (12). The word line driver circuit is capable of selecting a plurality of word lines simultaneously to permit writing into memory cells in a plurality of rows via the same bit line simultaneously. Cell strength control circuitry (17) reduces a drive strength required to write data into the cells, relative to a drive strength of the bit line driver circuits (15), at least during writing data into memory cells in a plurality of rows of memory cells. Preferably, the drive strength control circuitry (17) contain a resistive element in the power supply lines of the memory cells in a column, so that the supply voltage of the cells in the column is increasingly reduced when more current is drawn during writing of more cells simultaneously.

摘要翻译： 字线驱动器电路（10）耦合到存储器矩阵的字线（18），例如内容寻址单元（12）的矩阵。 字线驱动电路能够同时选择多个字线，以允许通过同一位线同时写入多行的存储单元。 至少在将数据写入多行存储器单元中的存储单元时，单元强度控制电路（17）相对于位线驱动电路（15）的驱动强度，将数据写入单元中所需的驱动强度降低 。 优选地，驱动强度控制电路（17）在列中的存储单元的电源线中包含电阻元件，使得当写入更多的电流时更多的电流被拉出时，列中的单元的电源电压逐渐减小 细胞同时进行。

公开(公告)号：US20050243639A1

公开(公告)日：2005-11-03

申请号：US10517586

申请日：2003-05-27

申请人： Roelof Salters

发明人： Roelof Salters

IPC分类号： G06F5/06 ,  G06F5/08 ,  G11C8/02

CPC分类号： G06F5/08

摘要： A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32′) of its successor (30′) share a common capacitive node (33).

摘要翻译： 根据本发明的FIFO寄存器（10）包括寄存器单元（10.1，...，10m）的序列，该寄存器单元具有数据段（40）和状态段（30）。 提供在输入（20）处的数据（Din）经由寄存器单元中的数据部分（40）移位到输出（50）。 每个单元的状态部分（30）指示该单元的数据段（40）是否包含有效数据。 单元的状​​态部分包括耦合到状态输入（32），状态输出（33）和时钟输入（31）的控制单元（37），并且产生输出时钟信号 控制与状态输入耦合的电荷控制元件（35,36）和状态输出，并控制数据部分（40）。 状态部分（30）的状态输出（33）和其后继（30'）的状态输入（32'）共享公共电容节点（33）。