公开(公告)号：US4951254A

公开(公告)日：1990-08-21

申请号：US272180

申请日：1988-11-16

申请人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

发明人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/00 ,  G06F11/22 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46

CPC分类号： G06F11/2273 ,  G01R31/31701 ,  G06F11/006 ,  G11C29/46

摘要： Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

摘要翻译： 具有多个测试模式的随机存取存储器单元，其被构造为集成电路，并且不包括特定的输入/输出引脚来定义和命令通过测试模式。 该单元配备有用于检测在通常使用的一组序列内但是其电压是否包括在指定的电压范围内的未包含的预定义逻辑信号序列的装置（1） 对于这样的信号，被提供给某些输入（CE，WE，AO），并且当检测到这样的序列时，将单元置于测试模式。 为了定义要执行的测试的性质，单元的地址输入端（A1-A8）连接到测试模式解码电路（2），其中将施加到所述输入端的数据用作 定义要执行的测试的性质的数据。

公开(公告)号：US5265064A

公开(公告)日：1993-11-23

申请号：US449666

申请日：1989-12-12

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/41 ,  H03K3/033 ,  H03K3/78 ,  H03K5/04 ,  H03K5/156 ,  G11C8/00

CPC分类号： H03K5/04 ,  H03K3/033 ,  H03K5/156

摘要： A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3). The circuit may be used as an equalisation pulse generator for a data path in a semiconductor memory integrated circuit.

公开(公告)号：US5224071A

公开(公告)日：1993-06-29

申请号：US390326

申请日：1989-08-07

申请人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C11/41 ,  G11C8/06

CPC分类号： G11C8/06

摘要： An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

摘要翻译： 可寻址存储器单元具有地址输入缓冲器电路，其输出一对输出连接，在读出或写入模式中，存在彼此互补的两个信号，但是也可以以这样的方式采用相等的值， 预解码器和线选择器来选择所有或没有选择线来控制所访问的存储器的单元。

公开(公告)号：US06751111B2

公开(公告)日：2004-06-15

申请号：US10227380

申请日：2002-08-26

申请人： Richard C. Foss ,  Cormac O'Connell

发明人： Richard C. Foss ,  Cormac O'Connell

IPC分类号： G11C1500

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C15/04 ,  G11C15/043

摘要： A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inerting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.

摘要翻译： 存储单元，包括反相级，耦合在数据线和反相级的输入端之间的存取晶体管，所述存取晶体管响应于选择性地耦合所述数据线和所述反相级输入的控制信号，耦合到 反相级输入并且响应于反相级的输出，用于在第一逻辑状态下锁存所述衰减级，并且由此流过所述存取晶体管的漏电流将所述单元保持在第二逻辑状态，所述漏电流大于电流 流过反馈晶体管。

公开(公告)号：US5694143A

公开(公告)日：1997-12-02

申请号：US253271

申请日：1994-06-02

申请人： Dennis Fielder ,  James Derbyshire ,  Peter Gillingham ,  Randy Torrance ,  Cormac O'Connell

发明人： Dennis Fielder ,  James Derbyshire ,  Peter Gillingham ,  Randy Torrance ,  Cormac O'Connell

IPC分类号： G06T1/20 ,  G06F3/153 ,  G06F12/00 ,  G06F13/16 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4093 ,  G11C11/4096 ,  H01L27/10

CPC分类号： G09G5/363 ,  G09G5/39 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/1048 ,  G11C2207/104

摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。