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    Chemically modified nonwoven articles and method for producing the same
    2.
    发明授权
    Chemically modified nonwoven articles and method for producing the same 失效
    化学改性非织造制品及其制备方法

    公开(公告)号：US06602437B1

    公开(公告)日：2003-08-05

    申请号：US10071335

    申请日：2002-02-08

    申请人： Brian C. Miller ,  Raymond C. Sturm

    发明人： Brian C. Miller ,  Raymond C. Sturm

    IPC分类号： D06M1500

    CPC分类号： D06M15/564 ,  D06M15/227 ,  D06M15/256 ,  D06M15/263 ,  D06M15/507 ,  D06M15/643 ,  D06M2200/35

    摘要： A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.

    摘要翻译： 提供了一种化学改性的非织造织物制品及其制备方法，其具有起球抗性，污垢释放，强度和耐磨性能，因此使制品不易形成令人不快的丸丸，染色或强度损失， 从而增加穿着者的舒适度并保持制品的期望外观，从而延长制品的使用寿命。 还提供了用于化学改性非织造织物制品以实现起球抗性，去污，强度和耐磨性的物质组合物。

    Low-power CMOS digital voltage level shifter
    3.
    发明授权
    Low-power CMOS digital voltage level shifter 有权
    低功耗CMOS数字电压电平转换器

    公开(公告)号：US06429683B1

    公开(公告)日：2002-08-06

    申请号：US09640259

    申请日：2000-08-16

    申请人： Darrin C. Miller ,  Brian C Miller

    发明人： Darrin C. Miller ,  Brian C Miller

    IPC分类号： H03K190185

    CPC分类号： H03K19/0013 ,  H03K19/018521

    摘要： An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.

    摘要翻译： 描述了通过反馈电路和上拉装置消除静态电流消耗的装置和方法，其将低电压摆幅数字信号转换为具有相对较高电压摆幅的相同极性的信号。 通过使用根据本发明的实施例，消耗的功率很小，并且作为用于FET降解的机制的热电子注入几乎不被关注。 另外，不需要专门的参考电压，电路的精确布局对于正确的电路性能并不重要。

    Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block
    4.
    发明授权
    Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block 失效
    用于生成嵌入在标准单元控制块中的规则结构的集成电路设计系统和方法

    公开(公告)号：US5847969A

    公开(公告)日：1998-12-08

    申请号：US641660

    申请日：1996-05-01

    申请人： Brian C. Miller ,  Peter J. Meier

    发明人： Brian C. Miller ,  Peter J. Meier

    IPC分类号： G06F17/50 ,  H01L27/118 ,  G06F17/00

    CPC分类号： H01L27/118 ,  G06F17/5068

    摘要： An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.

    摘要翻译： 提供了一种改进的系统和方法，用于产生常规结构的设计，例如嵌入在标准单元控制块（SCCB）中的存储器阵列，乘法器阵列或加法器阵列。 一旦通过逻辑综合工具为SCCB生成了网络列表，就会为常规结构的元素创建一个特殊类别的单元格。 通过向特殊类的单元格添加一个或多个专门用于优化常规结构单元格放置的特殊属性，可以通过特殊的类机制修改网络列表。 修改的布局和布线工具通过读取和解释特殊属性来处理修改的网络列表，以便为SCCB生成改进的设计。

    Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor
    5.
    发明授权
    Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor 失效
    具有最小逻辑多路复用器系统的图形加速器，用于共享微处理器

    公开(公告)号：US5796288A

    公开(公告)日：1998-08-18

    申请号：US730170

    申请日：1996-10-15

    申请人： Alan S. Krech, Jr. ,  Brian C. Miller

    发明人： Alan S. Krech, Jr. ,  Brian C. Miller

    IPC分类号： G06F7/00 ,  G06F15/78 ,  G09G5/39 ,  H03K17/00 ,  H03K19/0175 ,  H03K17/693

    CPC分类号： H03K17/005 ,  G09G5/39

    摘要： A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

    摘要翻译： 使用具有单热启用引线的三态驱动器的最小逻辑多路复用器系统通过多个控制单元中的任何一个提供对处理器元件的高速访问。 多路复用器系统以使电路实现最小化的方式实现，使电路实现内的门延迟最小化，并且允许处理指令通过其间的复用控制线从控制单元传递到处理器元件。 多路复用器系统包含通过选择引线并联启用和禁用的控制单元门组。 每个控制单元门组可以在相应的控制单元内部实现，或者在公共中间多路复用器电路位置中被外部实现。

    Dual transparent latch
    6.
    发明授权
    Dual transparent latch 失效
    双透明闩锁

    公开(公告)号：US5424996A

    公开(公告)日：1995-06-13

    申请号：US953158

    申请日：1992-09-29

    申请人： Robert J. Martin ,  Glenn T. Colon-Bonet ,  Brian C. Miller

    发明人： Robert J. Martin ,  Glenn T. Colon-Bonet ,  Brian C. Miller

    IPC分类号： G11C7/10 ,  G11C8/06 ,  H03K3/012 ,  H03K3/037 ,  G11C8/00 ,  G11C7/00

    CPC分类号： H03K3/037 ,  G11C7/1078 ,  G11C8/06 ,  H03K3/012

    摘要： A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed. A method for generating a master signal having a master frequency and selectively enabling inputs at an input data rate greater than the master frequency to input data into memory and selectively enabling outputs at the input data rate to output data from memory.

    摘要翻译： 公开了一种双透明锁存电路，其包括由两个控制线交叉耦合在一起的两个锁存器，以使得锁存器能够共同地以主控制器频率的频率的两倍输入和输出，该时钟频率分别控制每个锁存器的定时。 控制线由时钟发生器控制，使得一个锁存器能够接收和存储数据，而另一个锁存器被使能以输出存储在其中的数据。 同时，禁止接收和存储数据的锁存器提供存储的数据的输出，并且提供输出的锁存器被禁止接收和存储数据。 时钟发生器切换控制线的状态，使得它们能够或禁止从主时钟信号的每个相位上的锁存器输入数据并输出数据。 还公开了具有三重边沿定时的双透明锁存器。 一种用于产生具有主频率的主信号并且以大于主频率的输入数据速率选择性地启用输入的方法，用于将数据输入到存储器中，并且以输入数据速率有选择地使得输出能够从存储器输出数据。

    Circuit for evaluating signal timing
    7.
    发明授权
    Circuit for evaluating signal timing 失效
    用于评估信号时序的电路

    公开(公告)号：US06073261A

    公开(公告)日：2000-06-06

    申请号：US83311

    申请日：1998-05-22

    申请人： Brian C. Miller

    发明人： Brian C. Miller

    IPC分类号： G01R31/30 ,  G01R31/3193 ,  G01R31/28

    CPC分类号： G01R31/31937 ,  G01R31/3016

    摘要： The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with this inventive aspect, the method includes the steps of selecting a first electrical signal to be evaluated and discretizing the selected electrical signal into a plurality of signal values closely spaced in time. This "discretizing" function is preferably achieved passing the selected signal through a plurality of cascaded delay or buffer elements, then loading the signal values output from each buffer element (at a given time instance) into a plurality of register elements. In this way, the register elements, collectively, contain a snapshot of the selected signal over a defined period of time. Finally, the method includes the step of evaluating the plurality of signal values.

    摘要翻译： 本发明一般涉及用于评估集成电路中的电信号的定时关系的电路和方法。 根据本发明的一个方面，提供了具有包括两个或多个输入和一个输出的信号选择电路的电路。 信号选择电路（优选多路复用器）被配置为选择两个或更多个输入信号中的一个用于评估并将其引导到输出。 多个信号缓冲器电连接到信号选择电路的输出端。 最后，设置具有多个扫描元件的扫描链以获取沿多个信号缓冲器的电信号的状态。 根据本发明的另一方面，提供了一种用于评估集成电路中的电信号的定时关系的方法。 根据本发明的方面，该方法包括以下步骤：选择待评估的第一电信号并将所选择的电信号离散成多个紧密间隔的信号值。 优选地，这种“离散化”功能是通过多个级联的延迟或缓冲元件传递所选择的信号，然后将从每个缓冲元件输出的信号值（在给定的时间实例）加载到多个寄存器元件中。 以这种方式，寄存器元件统一地在所定义的时间段内包含所选信号的快照。 最后，该方法包括评估多个信号值的步骤。

    Chemically modified nonwoven articles and method for producing the same
    10.
    发明授权
    Chemically modified nonwoven articles and method for producing the same 失效
    化学改性非织造制品及其制备方法

    公开(公告)号：US06673125B2

    公开(公告)日：2004-01-06

    申请号：US10071297

    申请日：2002-02-08

    申请人： Brian C. Miller ,  Raymond C. Sturm

    发明人： Brian C. Miller ,  Raymond C. Sturm

    IPC分类号： D06M15643

    CPC分类号： D06M15/643 ,  D06M15/227 ,  D06M15/256 ,  D06M15/263 ,  D06M15/507 ,  D06M15/564 ,  D06M2200/35 ,  Y10T442/2279 ,  Y10T442/2287 ,  Y10T442/241

    摘要： A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.

    摘要翻译： 提供了一种化学改性的非织造织物制品及其制备方法，其具有起球抗性，污垢释放，强度和耐磨性能，因此使制品不易形成令人不快的丸丸，染色或强度损失， 从而增加佩戴者的舒适度并保持制品的期望外观，从而延长制品的使用寿命。 还提供了用于化学改性非织造织物制品以实现起球抗性，去污，强度和耐磨性的物质组合物。