公开(公告)号：US20060125759A1

公开(公告)日：2006-06-15

申请号：US11294080

申请日：2005-12-05

申请人： Chang-Ho An

发明人： Chang-Ho An

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/0252

摘要： Provided is an output buffer for a source driver of an LCD with a high slew rate, and a method of controlling the output buffer. The output buffer, which outputs a source line driving signal for driving a source line of the LCD, includes: an amplifier section amplifying an analog image signal; an output section outputting the source line driving signal in response to a signal amplified by the amplifier section; and a slew rate controller section, setting a capacitance of a capacitor section to a first capacitance, during a first charge sharing period in which the source line is precharged to a first precharge voltage, setting the capacitance of the capacitor section to a second capacitance smaller than the first capacitance during a second charge sharing period in which the source line driving signal is supplied to the source line, and setting the capacitance of the capacitor section to the first capacitance while the source line driving signal is maintained after the second charge sharing period.

摘要翻译： 提供了一种用于具有高压摆率的LCD的源极驱动器的输出缓冲器，以及控制输出缓冲器的方法。 输出用于驱动LCD的源极线的源极线驱动信号的输出缓冲器包括：放大模拟图像信号的放大器部; 输出部分，响应于由放大器部分放大的信号，输出源极线驱动信号; 以及转换速率控制器部分，在将源极线预充电到第一预充电电压的第一电荷共享周期期间将电容器部分的电容设置为第一电容，将电容器部分的电容设置为较小的第二电容 比在源极线驱动信号被提供给源极线的第二电荷共享期间的第一电容，并且在第二电荷共享期间保持源极线驱动信号之后将电容器部分的电容设置为第一电容 。

公开(公告)号：US08350797B2

公开(公告)日：2013-01-08

申请号：US12217781

申请日：2008-07-09

申请人： Junho Song ,  Chang-Ho An ,  Chul-Ho Choi ,  Min-Sung Kim ,  Mi-Ran Kim

发明人： Junho Song ,  Chang-Ho An ,  Chul-Ho Choi ,  Min-Sung Kim ,  Mi-Ran Kim

IPC分类号： G09G3/36

CPC分类号： H03F3/4521 ,  G09G3/3685 ,  G09G2310/0291 ,  G09G2330/021 ,  H03F1/0211 ,  H03F3/3022 ,  H03F2200/411 ,  H03F2200/516 ,  H03F2203/45648

摘要： A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

公开(公告)号：US08264262B2

公开(公告)日：2012-09-11

申请号：US12950380

申请日：2010-11-19

申请人： Chang-ho An

发明人： Chang-ho An

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.

摘要翻译： 提供了延迟锁定环路（DDL）电路和包括该延迟锁定环路的半导体器件。 DDL电路包括：控制电压发生器，用于通过将输入时钟与顺序生成并具有不同延迟的多个比较时钟进行比较来产生对应于输入时钟和多个比较时钟之间的延迟差的控制电压; 脉冲宽度调节器，用于根据输入时钟和比较时钟的任意比较时钟之间的延迟差来调节输入时钟的脉冲宽度，并产生脉冲宽度调整的输入时钟作为经调整的输入时钟; 以及延迟单元，用于响应于控制电压延迟调整的输入时钟，并用于输出延迟调整的输入时钟作为比较时钟和输出时钟。

公开(公告)号：US20090224830A1

公开(公告)日：2009-09-10

申请号：US12468124

申请日：2009-05-19

申请人： Chang Ho An ,  Si Wang Sung

发明人： Chang Ho An ,  Si Wang Sung

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/3023 ,  H03F3/45192 ,  H03F3/45475 ,  H03F2203/30015 ,  H03F2203/45138 ,  H03F2203/45626 ,  H03F2203/45726

摘要： An operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first switch connected between a first power source and an output node and switched in response to a voltage of a first output terminal of the differential amplifier, a first bias circuit to control an amount of a reference current flowing in the first branch in response to a voltage of a second output terminal of the differential amplifier, a second bias circuit to control a voltage of the second branch in which a mirror current flows, in response to a voltage of the first output terminal, a second switch connected between the output node and a second power source and switched in response to a voltage of the second branch, and a capacitor connected between the output node and the first output terminal.

摘要翻译： 运算放大器包括：差分放大器，包括有源负载，包括第一分支和第二分支的电流镜;连接在第一电源和输出节点之间的第一开关，并响应于第一输出端的电压而被切换 差分放大器，用于响应于差分放大器的第二输出端的电压来控制在第一分支中流动的参考电流的量的第一偏置电路，用于控制第二分支的电压的第二偏置电路，其中 反射镜电流响应于第一输出端子的电压而流动，第二开关连接在输出节点和第二电源之间，并且响应于第二分支的电压而被切换，以及连接在输出节点和 第一个输出端子。

公开(公告)号：US08466909B2

公开(公告)日：2013-06-18

申请号：US12941459

申请日：2010-11-08

申请人： Chang-ho An ,  Jae-wook Kwon ,  Ki-won Seo ,  Sung-ho Lee

发明人： Chang-ho An ,  Jae-wook Kwon ,  Ki-won Seo ,  Sung-ho Lee

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3688 ,  G09G2320/0252

摘要： An output buffer having a high slew rate, a method of controlling the output buffer, and a display driving device including the output buffer. The output buffer includes: a first output buffer adapted to output a source line driving signal to a first output terminal in response to a first control signal and output a source driving signal to a second output terminal in response to a second control signal; a second output buffer adapted to output a source line driving signal to a third output terminal in response to the first control signal and output a source line driving signal to a fourth output terminal in response to the second control signal; and a feedback circuit for connecting the first through fourth output terminals to negative input terminals of the first and second output buffers in response to the first control signal and the second control signal.

摘要翻译： 具有高压摆率的输出缓冲器，控制输出缓冲器的方法以及包括输出缓冲器的显示驱动装置。 输出缓冲器包括：第一输出缓冲器，用于响应于第一控制信号将源极线驱动信号输出到第一输出端，​​并响应于第二控制信号将源驱动信号输出到第二输出端; 第二输出缓冲器，用于响应于所述第一控制信号将源极线驱动信号输出到第三输出端，并响应于所述第二控制信号将源极线驱动信号输出到第四输出端; 以及反馈电路，用于响应于第一控制信号和第二控制信号将第一至第四输出端连接到第一和第二输出缓冲器的负输入端。

公开(公告)号：US20120127386A1

公开(公告)日：2012-05-24

申请号：US13304473

申请日：2011-11-25

申请人： Jae-wook Kwon ,  Chang-ho An ,  Ki-won Seo ,  Sung-ho Lee

发明人： Jae-wook Kwon ,  Chang-ho An ,  Ki-won Seo ,  Sung-ho Lee

IPC分类号： G02F1/136 ,  H03K17/00

CPC分类号： G09G3/3688 ,  G09G3/006 ,  G09G2310/0297

摘要： A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.

摘要翻译： 多通道半导体器件包括多个缓冲器组，每个缓冲器组包括至少一个输出缓冲器，每个包括至少一个输出焊盘的多个焊盘组以及控制多个缓冲器组与多个缓冲器组之间的连接的通道切换部分 的垫组。 其中一个焊盘组以第一操作模式输出一个缓冲组的输出信号，并在第二操作模式中顺序地输出所有缓冲组的输出信号。

公开(公告)号：US20110128056A1

公开(公告)日：2011-06-02

申请号：US12950380

申请日：2010-11-19

申请人： Chang-ho AN

发明人： Chang-ho AN

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.

摘要翻译： 提供了延迟锁定环路（DDL）电路和包括该延迟锁定环路的半导体器件。 DDL电路包括：控制电压发生器，用于通过将输入时钟与顺序生成并具有不同延迟的多个比较时钟进行比较来产生对应于输入时钟与多个比较时钟之间的延迟差的控制电压; 脉冲宽度调节器，用于根据输入时钟和比较时钟的任意比较时钟之间的延迟差来调节输入时钟的脉冲宽度，并产生脉冲宽度调整的输入时钟作为经调整的输入时钟; 以及延迟单元，用于响应于控制电压延迟调整的输入时钟，并用于输出延迟调整的输入时钟作为比较时钟和输出时钟。

公开(公告)号：US07859505B2

公开(公告)日：2010-12-28

申请号：US11294080

申请日：2005-12-05

申请人： Chang-Ho An

发明人： Chang-Ho An

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/0252

摘要： Provided is an output buffer for a source driver of an LCD with a high slew rate, and a method of controlling the output buffer. The output buffer, which outputs a source line driving signal for driving a source line of the LCD, includes: an amplifier section amplifying an analog image signal; an output section outputting the source line driving signal in response to a signal amplified by the amplifier section; and a slew rate controller section, setting a capacitance of a capacitor section to a first capacitance, during a first charge sharing period in which the source line is precharged to a first precharge voltage, setting the capacitance of the capacitor section to a second capacitance smaller than the first capacitance during a second charge sharing period in which the source line driving signal is supplied to the source line, and setting the capacitance of the capacitor section to the first capacitance while the source line driving signal is maintained after the second charge sharing period.

摘要翻译： 提供了一种用于具有高压摆率的LCD的源极驱动器的输出缓冲器，以及控制输出缓冲器的方法。 输出用于驱动LCD的源极线的源极线驱动信号的输出缓冲器包括：放大模拟图像信号的放大器部; 输出部分，响应于由放大器部分放大的信号，输出源极线驱动信号; 以及转换速率控制器部分，在将源极线预充电到第一预充电电压的第一电荷共享周期期间将电容器部分的电容设置为第一电容，将电容器部分的电容设置为较小的第二电容 比在源极线驱动信号被提供给源极线的第二电荷共享期间的第一电容，并且在第二电荷共享期间保持源极线驱动信号之后将电容器部分的电容设置为第一电容 。

公开(公告)号：US07764121B2

公开(公告)日：2010-07-27

申请号：US12217933

申请日：2008-07-10

申请人： Chang Ho An ,  Kye Eon Chang

发明人： Chang Ho An ,  Kye Eon Chang

IPC分类号： H03F3/45

CPC分类号： H03F3/45219 ,  H03F3/3022 ,  H03F3/4521 ,  H03F2203/45091 ,  H03F2203/45301 ,  H03F2203/45302 ,  H03F2203/45726

摘要： A differential amplifier includes input, output, current summing, and switch circuits. The input circuit generates first and second differential currents in response to a voltage difference between differential input signals. The output circuit includes a first and second transistors connected between a first voltage rail and output port and the output port and second voltage rail, respectively. The current summing circuit includes a first control node outputting a first control voltage to control a current in the first transistor and a second control node outputting a second control voltage to control a current in the second transistor, in response to the first and second differential currents, respectively. The switch circuit connects the first transistor gate to one of the first control node and the first voltage rail and the second transistor gate to one of the second control node and the second voltage rail, in response to a control signal.

摘要翻译： 差分放大器包括输入，输出，电流求和和开关电路。 输入电路响应于差分输入信号之间的电压差产生第一和第二差分电流。 输出电路包括分别连接在第一电压轨和输出口与输出端口和第二电压轨之间的第一和第二晶体管。 电流求和电路包括：第一控制节点，输出第一控制电压以控制第一晶体管中的电流;以及第二控制节点，响应于第一和第二差分电流，输出第二控制电压以控制第二晶体管中的电流 ， 分别。 响应于控制信号，开关电路将第一晶体管栅极连接到第一控制节点和第一电压轨之一以及第二晶体管栅极连接到第二控制节点和第二电压轨之一。

公开(公告)号：US07760199B2

公开(公告)日：2010-07-20

申请号：US11443308

申请日：2006-05-31

申请人： Chang-Ho An

发明人： Chang-Ho An

IPC分类号： G06F3/38

CPC分类号： H03F3/45219 ,  H03F2203/45471 ,  H03F2203/45506

摘要： A source driver employed in a liquid crystal display device uses a slew-rate control signal to regulate a slew rate of its output buffers, which makes an output voltage selectively operable at a low slew rate. Such a source driver can reduce (if not prevent) distortion of a common voltage.

摘要翻译： 在液晶显示装置中使用的源极驱动器使用压摆率控制信号来调节其输出缓冲器的转换速率，这使输出电压以低压摆率选择性地工作。 这样的源极驱动器可以减小（如果不是防止）公共电压的失真。