利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.018 秒)

    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
    1.
    发明申请
    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
    具有降低功率的高级存储器件和改进的性能

    公开(公告)号：US20100220536A1

    公开(公告)日：2010-09-02

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES
    2.
    发明申请
    276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 审中-公开
    具有增强的存储器系统的276引脚缓冲存储器模块互连和特性

    公开(公告)号：US20100005220A1

    公开(公告)日：2010-01-07

    申请号：US12166208

    申请日：2008-07-01

    申请人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    发明人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    IPC分类号： G06F12/06 ,  G06F12/10

    CPC分类号： G06F13/426

    摘要： A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses.

    摘要翻译： 一种存储器模块，其包括以一个或多个等级排列的第一组存储器件和布置在一个或多个等级中的第二组存储器件。 存储器模块还包括第一和第二端口，其中第一端口可与第二端口同时且独立于第二端口操作。 存储器模块还包括与第一端口和第一组存储器设备通信的第一存储器设备总线，以及与第二端口和第二组存储器设备通信的第二存储器设备总线。 存储器模块还包括被配置为重新驱动级联互连系统中的信息的集线器设备。 集线器设备包括用于经由第一和第二端口以及第一和第二存储器设备总线从存储器设备的级别读取数据并将数据写入存储器设备的逻辑。

    276-pin buffered memory module with enhanced memory system interconnect and features
    5.
    发明授权
    276-pin buffered memory module with enhanced memory system interconnect and features 有权
    276针缓冲内存模块，具有增强的内存系统互连和功能

    公开(公告)号：US07717752B2

    公开(公告)日：2010-05-18

    申请号：US12166227

    申请日：2008-07-01

    申请人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    发明人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    IPC分类号： H01R24/00

    CPC分类号： G11C5/04 ,  H01R12/721

    摘要： A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.

    摘要翻译： 一种存储器子系统，包括具有第一侧和第二侧的矩形印刷电路卡，长度在149.5和153.5毫米之间，第一和第二端具有小于该长度的宽度。 存储器系统还包括在第一侧上沿着延长卡的长度的卡的第一边缘延伸的第一多个销，以及在卡的第一边缘上延伸的第二侧上的第二多个销。 存储系统还包括定位键，其中心位于卡的第一边缘上，并位于距离卡的第一端84.5至88.5毫米之间，并位于距卡的第二端62.5至66.5毫米之间。

    276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES
    6.
    发明申请
    276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 审中-公开
    具有增强的存储器系统的276引脚缓冲存储器模块互连和特性

    公开(公告)号：US20100005219A1

    公开(公告)日：2010-01-07

    申请号：US12166185

    申请日：2008-07-01

    申请人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    发明人： Karl D. Loughner ,  Kevin C. Gower ,  Charles A. Kilmer ,  Warren E. Maule

    IPC分类号： G06F12/06 ,  G06F11/00

    CPC分类号： G11C5/04 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/02 ,  G11C7/04 ,  G11C29/022

    摘要： A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices.

    摘要翻译： 一种存储模块，包括多个存储器通道连接器，用于经由多个高速通道与存储器控制器进行通信。 存储器模块还包括以一个或多个等级排列的多个存储器件，以及多个可独立操作的集线器器件。 每个集线器设备包括用于经由一个或多个存储器通道连接器从高速通道中的一个上接收信号并将信号驱动到存储器控制器的接口。 每个集线器设备还包括多个可独立操作的端口，以与存储器设备的所有等级的全部或一部分进行通信。