公开(公告)号：US09043171B2

公开(公告)日：2015-05-26

申请号：US13596063

申请日：2012-08-28

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

IPC: G01R21/00 ,  G06F17/50 ,  G01R21/06

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method for calculating efficiency of a power supply system includes: displaying a parameter selection interface on the display unit for selecting power supply parameters and transmission line parameters. Obtaining power supply parameters and transmission line parameters selected by the user via the parameter selection interface when determining the user has finished the selection. Determining a efficiency of a selected power supply of the power supply parameters according to the relationship table, and calculating a sum efficiency according to the obtained power supply parameters and the transmission line parameters and the efficiency of the selected power supply. And calculating a total efficiency of the power supply system according to each sum efficiency when determining that all of the power supplies of the power supply system have been selected.

Abstract translation: 一种用于计算电源系统的效率的方法包括：在显示单元上显示参数选择界面，用于选择电源参数和传输线参数。 当确定用户已经完成选择时，通过参数选择界面获取用户选择的电源参数和传输线参数。 根据关系表确定电源参数的选定电源的效率，并根据获得的电源参数和传输线参数以及所选择的电源的效率来计算总和效率。 并且当确定已经选择了电源系统的所有电源时，根据每个总效率来计算电力供应系统的总效率。

公开(公告)号：US08941232B2

公开(公告)日：2015-01-27

申请号：US13034263

申请日：2011-02-24

Applicant: You-Hua Chou ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Perre Kao

Inventor： You-Hua Chou ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Perre Kao

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L23/473 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/48 ,  H01L23/488 ,  H01L24/11 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11849 ,  H01L2224/16145 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.

Abstract translation: 用于形成连接到本文所述的冷却装置（或散热器）的金属凸块的机构使得具有装置的基板能够更有效地散发产生的热量。 此外，金属凸块允许定制凹凸设计以满足不同芯片的需要。 此外，半导体芯片和冷却装置之间的金属凸块的使用能够通过在凸块之间传递冷却流体而进行先进的冷却。

公开(公告)号：US08781783B2

公开(公告)日：2014-07-15

申请号：US12700747

申请日：2010-02-05

Applicant: Hsien-Chuan Liang ,  Shen-Chun Li ,  Chun-Jen Chen ,  Shou-Kuo Hsu ,  Yung-Chieh Chen ,  Wen-Laing Tseng

Inventor： Hsien-Chuan Liang ,  Shen-Chun Li ,  Chun-Jen Chen ,  Shou-Kuo Hsu ,  Yung-Chieh Chen ,  Wen-Laing Tseng

IPC: G01R31/00

CPC classification number: G01R31/2806 ,  G01R31/2834

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract translation: 用于检查印刷电路板（PCB）的控制芯片的接地通路的系统和方法提供了显示PCB布局的图形用户界面（GUI）。 控制芯片具有多个接地引脚。 计算机沿每个接地引脚的每个信号路径路由搜索每个接地引脚和接地通孔的信号路径路由。 如果有任何接地通孔具有相同的绝对坐标，则计算机确定接地通孔由多个接地引脚共用。

公开(公告)号：US08717112B2

公开(公告)日：2014-05-06

申请号：US13338268

申请日：2011-12-28

Applicant: Hong-Yeh Chang ,  Yuan-Ta Chiu ,  Chia-Hung Chang ,  Chun-Jen Chen

Inventor： Hong-Yeh Chang ,  Yuan-Ta Chiu ,  Chia-Hung Chang ,  Chun-Jen Chen

IPC: H03B1/00

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B27/00

Abstract: An inductance-capacitance (LC) oscillator including a first varactor cell, a first transistor, a second transistor and a first pair of differential transformers is provided. The first varactor cell provides a first variable capacitance to adjust/tune the frequency of a first differential oscillation signal generated by the LC oscillator, and outputting the first differential oscillation signal. The first transistor is coupled between a core dc supply voltage and a first terminal of the first varactor cell. The second transistor is coupled between a ground potential and a second terminal of the first varactor cell. The first pair of differential transformers is connected in cascade with the first transistor and the second transistor between the core dc supply voltage and the ground potential, and is used for increasing the output-swing of the first differential oscillation signal, and making a current flowing through the first transistor to be reused by the second transistor.

Abstract translation: 提供包括第一变容二极管单元，第一晶体管，第二晶体管和第一对差动变压器的电感 - 电容（LC）振荡器。 第一变容二极管单元提供第一可变电容以调整/调谐由LC振荡器产生的第一差分振荡信号的频率，并输出第一差分振荡信号。 第一晶体管耦合在核心直流电源电压和第一变容二极管单元的第一端子之间。 第二晶体管耦合在第一变容二极管单元的地电位和第二端之间。 第一对差动变压器与核心直流电源电压和地电位之间的第一晶体管和第二晶体管级联连接，并用于增加第一差分振荡信号的输出摆幅，并使电流流动 通过第一晶体管被第二晶体管重新使用。

公开(公告)号：US08604954B2

公开(公告)日：2013-12-10

申请号：US13596744

申请日：2012-08-28

Applicant: Chun-Jen Chen ,  Tsung-Heng Tsai ,  Tzu-Yi Tang

Inventor： Chun-Jen Chen ,  Tsung-Heng Tsai ,  Tzu-Yi Tang

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/1215

Abstract: A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC) is provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew.

Abstract translation: 提供了一种用于时间交织的模数转换器（ADC）的定时校准电路。 定时校准电路包括相关单元，自适应滤波器和延迟单元。 相关单元根据第一数字数据和第二数字数据之间的第一过零可能性分布产生第一相关系数，并且根据第二数字数据和第二数字数据之间的第二过零可能性分布产生第二相关系数 第三个数字数据。 自适应滤波器根据第一相关系数和第二相关系数之间的差产生预测的时间偏差。 延迟单元根据预测的时间偏差校准ADC的时钟信号。

公开(公告)号：US08536852B2

公开(公告)日：2013-09-17

申请号：US12730225

申请日：2010-03-23

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

IPC: G05F3/30

CPC classification number: G06F1/26 ,  Y10T307/414 ,  Y10T307/549

Abstract: A current balance circuit includes a first and a second current sensors, an averager, a first and a second control modules, and a first and a second rheostat elements. The first and second current sensors receive a first current and a second current from a power source respectively and convert the first and second currents into a first and a second voltages. The averager receives the first and second voltages and calculates to obtain an average voltage. The first and second control modules receive the first voltage, the second voltage, and the average voltage, to obtain a first and a second control signals, to control current conduction ability of the first and second rheostat elements, to make the first and second currents keep a dynamic balance.

Abstract translation: 电流平衡电路包括第一和第二电流传感器，平均器，第一和第二控制模块以及第一和第二变阻器元件。 第一和第二电流传感器分别接收来自电源的第一电流和第二电流，并将第一和第二电流转换成第一和第二电压。 平均器接收第一和第二电压并计算得到平均电压。 第一和第二控制模块接收第一电压，第二电压和平均电压，以获得第一和第二控制信号，以控制第一和第二变阻器元件的电流传导能力，以使第一和第二电流 保持动态平衡。

公开(公告)号：US20130204558A1

公开(公告)日：2013-08-08

申请号：US13596063

申请日：2012-08-28

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: G06F19/00 ,  G01R21/06

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method for calculating efficiency of a power supply system includes: displaying a parameter selection interface on the display unit for selecting power supply parameters and transmission line parameters. Obtaining power supply parameters and transmission line parameters selected by the user via the parameter selection interface when determining the user has finished the selection. Determining a efficiency of a selected power supply of the power supply parameters according to the relationship table, and calculating a sum efficiency according to the obtained power supply parameters and the transmission line parameters and the efficiency of the selected power supply. And calculating a total efficiency of the power supply system according to each sum efficiency when determining that all of the power supplies of the power supply system have been selected.

Abstract translation: 一种用于计算电源系统的效率的方法包括：在显示单元上显示参数选择界面，用于选择电源参数和传输线参数。 当确定用户已经完成选择时，通过参数选择界面获取用户选择的电源参数和传输线参数。 根据关系表确定电源参数的选定电源的效率，并根据获得的电源参数和传输线参数以及所选择的电源的效率来计算总和效率。 并且当确定已经选择了电源系统的所有电源时，根据每个总效率来计算电力供应系统的总效率。

公开(公告)号：US20130093475A1

公开(公告)日：2013-04-18

申请号：US13339361

申请日：2011-12-28

Applicant: Hong-Yeh Chang ,  Yen-Liang Yeh ,  Chia-Hung Chang ,  Chun-Jen Chen

Inventor： Hong-Yeh Chang ,  Yen-Liang Yeh ,  Chia-Hung Chang ,  Chun-Jen Chen

IPC: H03B19/12

CPC classification number: H03B19/14 ,  H03B2200/0074

Abstract: An injection-locked frequency divider (ILFD) including a signal injector, an oscillator (OSC), and a buffer stage is provided. The signal injector is configured for receiving an injection signal. The OSC is configured for dividing the frequency of the injection signal, so as to generate a first divided frequency signal, where there is an integral-multiple relation between the frequency of the first divided frequency signal and that of the injection signal. The buffer stage is configured for receiving and boosting the first divided frequency signal, and performing a push-push process on the first divided frequency signal, so as to output a second divided frequency signal, where there is a fractional-multiple relation between the frequency of the second divided frequency signal and that of the injection signal.

Abstract translation: 提供了包括信号注入器，振荡器（OSC）和缓冲器级的注入锁定分频器（ILFD）。 信号注射器被配置为接收注入信号。 OSC被配置为用于分割喷射信号的频率，以便产生第一分频信号，其中在第一分频信号的频率与喷射信号的频率之间存在整数倍关系。 缓冲级被配置为接收和升压第一分频信号，并且对第一分频信号执行推推处理，以便输出第二分频信号，其中频率之间存在小数倍关系 的第二分频信号和注入信号的信号。

公开(公告)号：US20130009715A1

公开(公告)日：2013-01-10

申请号：US13338268

申请日：2011-12-28

Applicant: Hong-Yeh Chang ,  Yuan-Ta Chiu ,  Chia-Hung Chang ,  Chun-Jen Chen

Inventor： Hong-Yeh Chang ,  Yuan-Ta Chiu ,  Chia-Hung Chang ,  Chun-Jen Chen

IPC: H03B5/12

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B27/00

Abstract: An inductance-capacitance (LC) oscillator including a first varactor cell, a first transistor, a second transistor and a first pair of differential transformers is provided. The first varactor cell provides a first variable capacitance to adjust/tune the frequency of a first differential oscillation signal generated by the LC oscillator, and outputting the first differential oscillation signal. The first transistor is coupled between a core dc supply voltage and a first terminal of the first varactor cell. The second transistor is coupled between a ground potential and a second terminal of the first varactor cell. The first pair of differential transformers is connected in cascade with the first transistor and the second transistor between the core dc supply voltage and the ground potential, and is used for increasing the output-swing of the first differential oscillation signal, and making a current flowing through the first transistor to be reused by the second transistor.

Abstract translation: 提供包括第一变容二极管单元，第一晶体管，第二晶体管和第一对差动变压器的电感 - 电容（LC）振荡器。 第一变容二极管单元提供第一可变电容以调整/调谐由LC振荡器产生的第一差分振荡信号的频率，并输出第一差分振荡信号。 第一晶体管耦合在核心直流电源电压和第一变容二极管单元的第一端子之间。 第二晶体管耦合在第一变容二极管单元的地电位和第二端之间。 第一对差动变压器与核心直流电源电压和地电位之间的第一晶体管和第二晶体管级联连接，并用于增加第一差分振荡信号的输出摆幅，并使电流流动 通过第一晶体管被第二晶体管重新使用。

公开(公告)号：US20130006561A1

公开(公告)日：2013-01-03

申请号：US13451433

申请日：2012-04-19

Applicant: PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  YING-TSO LAI ,  EN-SHUO CHANG

Inventor： PO-CHUAN HSIEH ,  CHUN-JEN CHEN ,  YING-TSO LAI ,  EN-SHUO CHANG

IPC: G06F19/00

CPC classification number: G06F17/5036 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/82

Abstract: In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification.

Abstract translation: 在使用计算设备分析印刷电路板（PCB）的信号组延迟的方法中，计算设备连接到从PCB的一对数据信号线和时钟信号线测量S参数的信号测量装置 。 该方法基于S参数分析数据信号线和时钟信号线的差分损耗系数，并根据差分损耗计算数据信号线的第一信号延迟和时钟信号线的第二信号延迟 系数。 该方法还根据第一信号延迟和第二信号延迟分析PCB的信号组延迟，并且如果信号组延迟不满足PCB设计规范，则在显示装置上显示信号组延迟。