公开(公告)号：US09859261B2

公开(公告)日：2018-01-02

申请号：US15465455

申请日：2017-03-21

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC分类号： H01L25/16 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/042 ,  H01L31/18 ,  H01L27/082 ,  H01L27/088 ,  H01L25/00

CPC分类号： H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

摘要： A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20170297903A1

公开(公告)日：2017-10-19

申请号：US15362199

申请日：2016-11-28

申请人： STATS ChipPAC Pte. Ltd.

发明人： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC分类号： B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L25/00

CPC分类号： B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

公开(公告)号：US20170249545A1

公开(公告)日：2017-08-31

申请号：US15515675

申请日：2015-09-30

申请人： Linxens Holding

发明人： Eric EYMARD ,  Cyril PROYE ,  Nicolas GUERINEAU

IPC分类号： G06K19/077

CPC分类号： G06K19/07749 ,  G06K19/067 ,  G06K19/077 ,  G06K19/07722 ,  G06K19/07747 ,  G06K19/0775 ,  G06K19/07754 ,  G06K19/07769 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15 ,  H01L2924/18161 ,  H01L2924/18165

摘要： A chip card manufacturing method. A module includes a substrate supporting contacts on one surface and conductive paths and a chip on another; and an antenna on a holder, the antenna including a contact pad for respectively connecting to each of the ends thereof. A solder drop is placed on each of the contact pads of the antenna. The holder of the antenna is inserted between plastic layers. A cavity is provided, in which the module can be accommodated and the solder drops remain accessible. The height of the solder drops before heating is suitable for projecting into the cavity. A module is placed in each cavity. The areas of the module that are located on the solder drops are heated to melt the solder and to solder the contact pads of the antenna to conductive paths of the module.

公开(公告)号：US20150076691A1

公开(公告)日：2015-03-19

申请号：US14487793

申请日：2014-09-16

申请人： LG INNOTEK CO., LTD.

发明人： Dong Sun KIM ,  Sung Wuk RYU ,  Ji Haeng LEE

IPC分类号： H01L23/00

CPC分类号： H01L24/12 ,  H01L23/49822 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/35 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball.

摘要翻译： 提供了一种半导体封装，包括：安装元件的下封装; 金属柱，其连接到所述下部封装并且包括至少一个金属材料部分; 以及安装元件的上部封装，并且经由焊球与金属柱连接。

公开(公告)号：US09899296B2

公开(公告)日：2018-02-20

申请号：US14593617

申请日：2015-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： You-Hua Chou ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Perre Kao

IPC分类号： H01L21/44 ,  H01L23/473 ,  H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/42

CPC分类号： H01L23/473 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/48 ,  H01L23/488 ,  H01L24/11 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11849 ,  H01L2224/16145 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

公开(公告)号：US20170243049A1

公开(公告)日：2017-08-24

申请号：US15477084

申请日：2017-04-01

申请人： SHENZHEN HUIDING TECHNOLOGY CO., LTD.

发明人： Haoxiang DONG

IPC分类号： G06K9/00 ,  A61B5/00 ,  H05K3/28 ,  H01L27/146 ,  H01L31/18 ,  H01L23/31 ,  H01L23/00 ,  H01L31/0203 ,  H05K3/06

CPC分类号： G06K9/00053 ,  A61B5/02416 ,  A61B5/0531 ,  A61B5/1172 ,  A61B5/14551 ,  A61B2562/04 ,  A61B2562/12 ,  A61B2562/166 ,  A61B2562/242 ,  A61B2562/247 ,  G06K9/0002 ,  G06K9/00114 ,  H01L27/14618 ,  H01L31/0203 ,  H01L31/18 ,  H01L2924/15 ,  H05K3/067 ,  H05K3/284 ,  H05K2201/09818

摘要： A package structure, an electronic device and a method for manufacturing the package structure are presented. The package structure comprises: a substrate (100), a sensing module (200) disposed on an upper surface of the substrate (100) and electrically connected to the substrate (100), and a package colloid (300) disposed on the upper surface of the substrate (100) and coating at least one portion of the sensing module (200), wherein the sensing module (200) comprises a capacitive sensor (210) and an optical sensor (220), and the package colloid (300) comprises at least one portion of a photic zone (310) disposed corresponding to the optical sensor (220). Thus, the capacitive sensor and the optical sensor can be packaged in one package structure, so as to improve the degree of integration of the package structure and save the package space.

公开(公告)号：US09611136B2

公开(公告)日：2017-04-04

申请号：US15169368

申请日：2016-05-31

申请人： Seiko Epson Corporation

发明人： Satoru Tanaka

IPC分类号： G01L9/00 ,  H01L21/00 ,  H05K7/02 ,  G01P15/08 ,  B81B3/00 ,  H01L23/00 ,  B81C1/00 ,  H01L23/528 ,  H01L21/762 ,  B81B7/00 ,  G01C19/5656

CPC分类号： B81B3/0072 ,  B81B3/0018 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81B2207/097 ,  B81C1/00158 ,  B81C2203/0109 ,  G01C19/5656 ,  G01L9/0042 ,  H01L21/76205 ,  H01L23/528 ,  H01L24/02 ,  H01L2224/0212 ,  H01L2924/15 ,  H01L2924/351

摘要： A functional element includes a substrate which is provided with a concave section; a stationary section connected to a wall section that defines the concave section of the substrate; an elastic section which extends from the stationary section and is capable of stretching and contracting in a first axis direction; a movable body connected to the elastic section; a movable electrode section which extends from the movable body. The concave section includes a cutout section which is provided on the wall section. The stationary section includes an overlap section which is spaced with the substrate, and overlaps the concave section when seen in a plan view. At least a portion of the overlap section overlaps the cutout section when seen in the plan view, and the elastic section extends from the overlap section.

公开(公告)号：US09508652B1

公开(公告)日：2016-11-29

申请号：US14950667

申请日：2015-11-24

申请人： HRL Laboratories, LLC

发明人： Florian G. Herrault ,  Melanie S. Yajima ,  Alexandros Margomenos

IPC分类号： H01L23/34 ,  H01L23/538 ,  H01L21/78 ,  H01L23/367 ,  H01L23/00 ,  H01L23/40

CPC分类号： H01L23/5389 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/40 ,  H01L23/66 ,  H01L24/11 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2223/6683 ,  H01L2224/1146 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81075 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81204 ,  H01L2224/81805 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15 ,  H01L2924/15159 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2224/83

摘要： A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.

摘要翻译： 一种用于晶片级封装的方法包括形成一个或多个管芯，在每个管芯上形成镀金属环（PMR），形成覆盖晶片（CW），CW具有一个或多个电镀密封环，形成体晶片（BW） BW在BW的第一侧具有空腔和金属层，将相应的管芯与CW对准，使得相应管芯上的PMR与CW上的相应的电镀密封环（PSR）对准，将PMR 在相应的芯片上相应的PSR，将BW与CW对准，使得BW的相应空腔围绕结合到CW的每个相应的芯片，并且使得BW上的金属层与CW上的至少一个PSR对准 并且将BW的第一侧上的金属层与CW上的PSR接合。 每个PMR具有第一高度，并且每个PSR具有第二高度。

公开(公告)号：US20160272483A1

公开(公告)日：2016-09-22

申请号：US15169368

申请日：2016-05-31

申请人： Seiko Epson Corporation

发明人： Satoru TANAKA

IPC分类号： B81B3/00

CPC分类号： B81B3/0072 ,  B81B3/0018 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81B2207/097 ,  B81C1/00158 ,  B81C2203/0109 ,  G01C19/5656 ,  G01L9/0042 ,  H01L21/76205 ,  H01L23/528 ,  H01L24/02 ,  H01L2224/0212 ,  H01L2924/15 ,  H01L2924/351

摘要： A functional element includes a substrate which is provided with a concave section; a stationary section connected to a wall section that defines the concave section of the substrate; an elastic section which extends from the stationary section and is capable of stretching and contracting in a first axis direction; a movable body connected to the elastic section; a movable electrode section which extends from the movable body. The concave section includes a cutout section which is provided on the wall section. The stationary section includes an overlap section which is spaced with the substrate, and overlaps the concave section when seen in a plan view. At least a portion of the overlap section overlaps the cutout section when seen in the plan view, and the elastic section extends from the overlap section.

摘要翻译： 功能元件包括设置有凹部的基板; 连接到限定所述基板的凹部的壁部的固定部; 弹性部分，其从固定部分延伸并且能够在第一轴线方向上伸缩; 连接到所述弹性部分的可移动体; 从可动体延伸的可动电极部。 凹部包括设置在壁部上的切口部。 固定部分包括与基板间隔开的重叠部分，并且在平面图中看时与凹部重叠。 当在平面图中看时，重叠部分的至少一部分与切口部分重叠，并且弹性部分从重叠部分延伸。

公开(公告)号：US20160241953A1

公开(公告)日：2016-08-18

申请号：US15043831

申请日：2016-02-15

申请人： Infineon Technologies AG

发明人： Klaus Elian ,  Horst Theuss ,  Thomas Mueller

IPC分类号： H04R1/40 ,  H04R1/04

CPC分类号： H04R1/083 ,  B81B7/0061 ,  B81B2201/0257 ,  H01L2224/95 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15 ,  H01L2924/181 ,  H01L2924/19106 ,  H04R1/04 ,  H04R1/406 ,  H04R19/005 ,  H04R2201/003 ,  H04R2410/05 ,  H04R2499/11

摘要： A surface mountable microphone package comprises a first microphone and a second microphone. Furthermore, the surface mountable microphone package comprises a first opening for the first microphone and a second opening for the second microphone. The first opening and the second opening are arranged on opposite sides of the surface mountable microphone package.