公开(公告)号：US20050227437A1

公开(公告)日：2005-10-13

申请号：US10821100

申请日：2004-04-07

Applicant: Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Yang

Inventor： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Yang

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/7881

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Abstract translation: 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。 结果，氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层，例如氧化硅层。 结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

公开(公告)号：US07387942B2

公开(公告)日：2008-06-17

申请号：US10732616

申请日：2003-12-09

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

IPC: H01L21/425 ,  H01L21/762

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

公开(公告)号：US20050170646A1

公开(公告)日：2005-08-04

申请号：US10772932

申请日：2004-02-04

Applicant: Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

Inventor： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC: H01L21/44 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract translation: 在集成电路制造中，使用具有侧向分量的蚀刻。 例如，蚀刻可以是各向同性的。 在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。 这种其他蚀刻可以是各向异性的。 该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。 该部分被各向异性蚀刻完全或部分地去除。 然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。 如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。 如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

公开(公告)号：US07910429B2

公开(公告)日：2011-03-22

申请号：US10821100

申请日：2004-04-07

Applicant: Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

Inventor： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/7881

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Abstract translation: 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。 结果，氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层，例如氧化硅层。 结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

公开(公告)号：US07300745B2

公开(公告)日：2007-11-27

申请号：US10772520

申请日：2004-02-04

Applicant: Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

Inventor： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L27/11539 ,  H01L27/115 ,  H01L27/11526

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract translation: 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。

公开(公告)号：US20060211255A1

公开(公告)日：2006-09-21

申请号：US11432222

申请日：2006-05-10

Applicant: Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

Inventor： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC: H01L21/302

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract translation: 在集成电路制造中，使用具有侧向分量的蚀刻。 例如，蚀刻可以是各向同性的。 在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。 这种其他蚀刻可以是各向异性的。 该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。 该部分被各向异性蚀刻完全或部分地去除。 然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。 如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。 如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

公开(公告)号：US06657281B1

公开(公告)日：2003-12-02

申请号：US09631755

申请日：2000-08-03

Applicant: Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

Inventor： Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

IPC: H01L27082

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

Abstract: The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

Abstract translation: 本发明提供一种位于半导体晶片基板上的双极晶体管。 双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层 。 例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。 然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

公开(公告)号：US07358149B2

公开(公告)日：2008-04-15

申请号：US11193150

申请日：2005-07-29

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

IPC: H01L21/425

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract translation: 衬底隔离沟槽（224）形成在半导体衬底（120）中。 通过离子注入将掺杂剂（例如硼）注入到沟槽侧壁中，以抑制沿着侧壁的电流泄漏。 在离子注入期间，晶体管栅极电介质（520）面向离子流，但在随后的热步骤中对栅极电介质的损坏退火。 在一些实施例中，掺杂剂注入是成角度的植入物。 植入物从晶片的相对侧进行，并且因此从每个有效区域的相对侧进行。 每个有源区域包括从一侧注入的区域和从相对侧注入的区域。 两个区域重叠以便于阈值电压调整。

公开(公告)号：US20070264776A1

公开(公告)日：2007-11-15

申请号：US11801301

申请日：2007-05-08

Applicant: Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

Inventor： Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

IPC: H01L21/336

CPC classification number: H01L29/511 ,  H01L29/40114

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

公开(公告)号：US20050124102A1

公开(公告)日：2005-06-09

申请号：US10732616

申请日：2003-12-09

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Kim

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract translation: 衬底隔离沟槽（224）形成在半导体衬底（120）中。 通过离子注入将掺杂剂（例如硼）注入到沟槽侧壁中，以抑制沿着侧壁的电流泄漏。 在离子注入期间，晶体管栅极电介质（520）面向离子流，但在随后的热步骤中对栅极电介质的损坏退火。 在一些实施例中，掺杂剂注入是成角度的植入物。 植入物从晶片的相对侧进行，并且因此从每个有效区域的相对侧进行。 每个有源区域包括从一侧注入的区域和从相对侧注入的区域。 两个区域重叠以便于阈值电压调整。