公开(公告)号：US06657281B1

公开(公告)日：2003-12-02

申请号：US09631755

申请日：2000-08-03

申请人： Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

发明人： Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

IPC分类号： H01L27082

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

摘要翻译： 本发明提供一种位于半导体晶片基板上的双极晶体管。 双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层 。 例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。 然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

公开(公告)号：US06537887B2

公开(公告)日：2003-03-25

申请号：US09727325

申请日：2000-11-30

申请人： Yih-Feng Chyan ,  Chung Wai Leung ,  Yi Ma ,  Demi Nguyen

发明人： Yih-Feng Chyan ,  Chung Wai Leung ,  Yi Ma ,  Demi Nguyen

IPC分类号： H01L218222

CPC分类号： H01L29/66272 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/8249 ,  H01L27/0623

摘要： An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

公开(公告)号：US06451660B1

公开(公告)日：2002-09-17

申请号：US09591037

申请日：2000-06-09

申请人： Yi Ma ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Jane Qian Liu ,  Timothy Scott Campbell

发明人： Yi Ma ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Jane Qian Liu ,  Timothy Scott Campbell

IPC分类号： H01L2131

CPC分类号： H01L29/66272 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/31675 ,  H01L29/0804

摘要： A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

摘要翻译： 双极器件（10）包括通过将表面浸入臭氧化去离子水中而在半导体衬底（12）的表面（16）上生长的氧化物层（24）。 通过选择水的适当温度和臭氧的浓度，可以将薄膜的厚度保持在大量的精细公差之内，并且在包含基底的晶片（W）的表面上。

公开(公告)号：US06815302B2

公开(公告)日：2004-11-09

申请号：US10028614

申请日：2001-12-21

申请人： Alan Sangone Chen ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Yi Ma ,  William John Nagy

发明人： Alan Sangone Chen ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Yi Ma ,  William John Nagy

IPC分类号： H01L218228

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/7375

摘要： The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

摘要翻译： 本发明提供一种制造双极晶体管的方法。 该方法可以包括在半导体晶片衬底中形成集电极，在集电极中形成基极，在所述集电极内部和底部上注入氧化物区域，并在衬底上形成发射极，使得氧化物区域位于发射极和发射极之间 的基地。

公开(公告)号：US06555871B1

公开(公告)日：2003-04-29

申请号：US09488108

申请日：2000-01-20

申请人： Yih-Feng Chyan ,  Chung Wai Leung ,  Ranbir Singh

发明人： Yih-Feng Chyan ,  Chung Wai Leung ,  Ranbir Singh

IPC分类号： H01L29792

CPC分类号： H01L27/11526 ,  H01L27/0623 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

摘要翻译： 本发明提供了一种双极晶体管，用于增加具有源极区和漏极区以及第一和第二互补阱的闪存单元的速度。 在一个实施例中，双极晶体管的基极位于第一互补槽中。 第一个辅助槽用作双极晶体管的集电极。 双极晶体管基极也独特地用作源极区域。 双极晶体管的发射极也位于第一个补充槽中，靠近基极。 例如，发射器可以位于基座附近或实际位于基底中。 在另外的实施例中，相对的基座和发射器位于快闪存储器单元的相对侧并且靠近闪存单元。

公开(公告)号：US06274490B1

公开(公告)日：2001-08-14

申请号：US09521268

申请日：2000-03-08

申请人： Yih-Feng Chyan ,  Yi Ma

发明人： Yih-Feng Chyan ,  Yi Ma

IPC分类号： H01L2144

CPC分类号： H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L21/76826 ,  H01L21/76834

摘要： The present invention provides a method of passivating a semiconductor device having a capping layer formed thereover, comprising: (1) subjecting the semiconductor device to a high pressure within a pressure chamber and (2) exposing the semiconductor device to a passivating gas. The high pressure causes the passivating gas, such as a deuterated passivating gas, to penetrate the capping layer and thereby passivate the semiconductor device. The method provided by the present invention is, therefore, particularly useful in those instances where a final passivation step is desired after the formation of the capping layer. It is believed that the hydrogen isotope bonds to dangling bond sites within the semiconductor device, which are most often present at a silicon/silicon dioxide interface. Further, because of their larger mass, these hydrogen isotope atoms are not easily removed by electron flow during the operation of the device as is the case with the lighter hydrogen atoms.

摘要翻译： 本发明提供一种钝化具有形成在其上的覆盖层的半导体器件的方法，包括：（1）使半导体器件在压力室内受到高压，以及（2）将半导体器件暴露于钝化气体。 高压使诸如氘代钝化气体的钝化气体穿透封盖层，从而钝化半导体器件。 因此，本发明提供的方法在形成覆盖层之后需要最终钝化步骤的情况下特别有用。 据信氢同位素结合到半导体器件内的悬挂键合位置，其通常存在于硅/二氧化硅界面处。 此外，由于它们的质量较大，与较轻的氢原子一样，这些氢同位素原子在器件的操作过程中不容易被电子流除去。

公开(公告)号：US06518622B1

公开(公告)日：2003-02-11

申请号：US09528753

申请日：2000-03-20

申请人： Hongzong Chew ,  Yih-Feng Chyan ,  John M. Hergenrother ,  Yi Ma ,  Donald P. Monroe

发明人： Hongzong Chew ,  Yih-Feng Chyan ,  John M. Hergenrother ,  Yi Ma ,  Donald P. Monroe

IPC分类号： H01L2976

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.

摘要翻译： 本发明提供一种形成在半导体晶片基板上的VRG结构。 VRG结构具有位于半导体晶片衬底中的第一源极/漏极区域和位于源极/漏极区域附近的导电层，第二源极/漏极区域和导电沟道，其从第一源极/漏极区域延伸到 第二源极/漏极区域。 导电层提供到第一源/漏区的电连接。 导电层可以具有低于第一源极/漏极区域的低电阻，其可以小于约50欧米亚/平方或小于约20欧米亚/平方。

公开(公告)号：US06358807B1

公开(公告)日：2002-03-19

申请号：US09504306

申请日：2000-02-15

申请人： Yih-Feng Chyan ,  Chung Leung

发明人： Yih-Feng Chyan ,  Chung Leung

IPC分类号： H01L21331

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/167

摘要： A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 1014 cm−2 before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

摘要翻译： 公开了一种BiCMOS半导体器件及其形成方法。 在半导体衬底内的CMOS器件区域附近形成双极晶体管区域。 在双极晶体管区域内形成基极，发射极和集电极之前，以约1013至约1014cm-2的量注入碳，以有助于抑制瞬时增强的扩散。 双极晶体管区域经受快速热退火，有助于抑制瞬时增强的扩散。

公开(公告)号：US6001701A

公开(公告)日：1999-12-14

申请号：US871385

申请日：1997-06-09

申请人： Michael Scott Carroll ,  Samir Chaudhry ,  Alan Sangone Chen ,  Yih-Feng Chyan ,  Kuo-Hua Lee ,  William John Nagy

发明人： Michael Scott Carroll ,  Samir Chaudhry ,  Alan Sangone Chen ,  Yih-Feng Chyan ,  Kuo-Hua Lee ,  William John Nagy

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L21/8249

CPC分类号： H01L29/66272 ,  H01L21/76218 ,  H01L21/8249 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/011

摘要： A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

摘要翻译： 公开了一种双极制造工艺，其示意性地适合于集成到常规CMOS工艺中，从而形成BiCMOS集成电路。 集电极和基极通过多个注入和单个掩模步骤形成，从而提供连续的低电阻集电区。

公开(公告)号：US06359317B1

公开(公告)日：2002-03-19

申请号：US09222587

申请日：1998-12-28

申请人： Michael S. Carroll ,  Yih-Feng Chyan ,  Samir Chaudhry ,  Tony G. Ivanov ,  Robert W. Dail ,  Alan S. Chen

发明人： Michael S. Carroll ,  Yih-Feng Chyan ,  Samir Chaudhry ,  Tony G. Ivanov ,  Robert W. Dail ,  Alan S. Chen

IPC分类号： H01L2976

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7322

摘要： A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

摘要翻译： 与CMOS处理兼容并且可用于互补BiMOS结构的双极性垂直PNP晶体管的特征在于其没有外延层并且采用高能注入磷层来提供N型衬底隔离。