公开(公告)号：US06804793B2

公开(公告)日：2004-10-12

申请号：US09811256

申请日：2001-03-16

Applicant: Don D Josephson ,  Samuel D. Naffziger

Inventor： Don D Josephson ,  Samuel D. Naffziger

IPC: G06F104

CPC classification number: G06F1/04

Abstract: A system and method are disclosed which provide an integrated circuit having a clock signal that is dynamically manipulated in response to detected events within the integrated circuit. In one embodiment, the chip includes event detection circuitry that monitors the operation of the chip and detects events that lead to a power disturbance therein. Circuitry may be included for detecting anticipated operation known to trigger an event, as well as for detecting unanticipated events. Additionally, clock manipulator circuitry is included to manipulate the chip's clock signal responsive detection of an event to enable the chip to cope with such event. In response to an event being detected, the clock manipulator circuitry may dynamically manipulate the clock signal in various manners, such as by altering the clock signal's duty cycle, delaying the occurrence of a transition of the clock signal, or altering the clock signal's frequency, as examples.

Abstract translation: 公开了一种系统和方法，其提供具有响应于集成电路内的检测到的事件动态地操纵的时钟信号的集成电路。 在一个实施例中，芯片包括事件检测电路，其监视芯片的操作并检测导致其中的功率干扰的事件。 可以包括用于检测已知触发事件的预期操作以及用于检测意外事件的电路。 此外，包括时钟操纵器电路以操纵芯片的时钟信号以响应事件的检测，以使芯片能够应对这种事件。 响应于检测到的事件，时钟操纵器电路可以以各种方式动态地操纵时钟信号，例如通过改变时钟信号的占空比，延迟时钟信号的转变的发生或改变时钟信号的频率， 作为例子。

公开(公告)号：US06484275B1

公开(公告)日：2002-11-19

申请号：US09449793

申请日：1999-11-26

Applicant: Don D Josephson ,  Daniel J Dixon ,  James S Finnell

Inventor： Don D Josephson ,  Daniel J Dixon ,  James S Finnell

IPC: H02H305

CPC classification number: G06F11/2733

Abstract: A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This test data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.

Abstract translation: 根据本发明的处理器包括存储测试数据和控制数据的存储器。 该处理器还包括将测试数据和控制数据从处理器的存储器传输到处理器的测试访问端口的测试应用程序。 然后，测试访问端口利用测试数据和控制数据捕获在处理器执行时定义处理器的至少一个状态的状态数据。 可以通过常规技术分析该测试数据，以检测和隔离处理器的执行中的错误。

公开(公告)号：US06509788B2

公开(公告)日：2003-01-21

申请号：US09811255

申请日：2001-03-16

Applicant: Samuel D. Naffziger ,  Don D Josephson

Inventor： Samuel D. Naffziger ,  Don D Josephson

IPC: H01J1982

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

公开(公告)号：US07250800B2

公开(公告)日：2007-07-31

申请号：US11179400

申请日：2005-07-12

Applicant: Quanhong Zhu ,  Don D. Josephson

Inventor： Quanhong Zhu ,  Don D. Josephson

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/05 ,  H03K2005/00156

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

公开(公告)号：US06397375B1

公开(公告)日：2002-05-28

申请号：US09507240

申请日：2000-02-18

Applicant: Adam Stuart Block ,  Jeffrey P Witte ,  Don D Josephson

Inventor： Adam Stuart Block ,  Jeffrey P Witte ,  Don D Josephson

IPC: G06F1750

CPC classification number: G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and system for managing metal resources in the physical design of integrated circuits is presented. Percent metal usage is allocated for intra-block routing use by each functional block. Power and clock grids are established. Block designers coordinate the locations of signal ports of the blocks so as to avoid blocking any inter-block signals, areas of metal are then reserved for ports and intra-block signals. The inter-block signals are then pre-routed, avoiding the power grid, clock grid, and reserved intra-block routing metal. If any problem nets emerge from the pre-routing, better port locations and sub-block placement within the respective blocks are determined and the process is repeated.

Abstract translation: 介绍了集成电路物理设计中管理金属资源的方法和系统。 百分比金属使用量被分配给每个功能块的块内路由使用。 功率和时钟网格建立。 块设计师协调块的信号端口的位置，以避免阻塞任何块间信号，然后将金属区域保留用于端口和块内信号。 块间​​信号然后被预先路由，避免了电网，时钟网格和保留的块内路由金属。 如果从预路由出现任何问题网络，则确定相应块内的更好的端口位置和子块布置，并重复该过程。

公开(公告)号：US5530706A

公开(公告)日：1996-06-25

申请号：US539382

申请日：1995-10-05

Applicant: Don D. Josephson ,  Barry J. Arnold

Inventor： Don D. Josephson ,  Barry J. Arnold

IPC: G01R31/3185 ,  G06F15/20 ,  H04B17/00

CPC classification number: G01R31/318577 ,  G01R31/318541

Abstract: A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.

Abstract translation: 一种用于数字集成电路的测试系统，其中在数字电路以正常时钟速度操作时非集成电路的内部状态被非破坏性地捕获。 用于捕获状态的单元被顺序地连接到移位寄存器中。 一旦内部状态被锁存在单元内，则捕获的状态在集成电路继续工作时，串行地移出测试端口。 状态采样通过软件命令内部触发，或通过与内部时钟同步的外部信号从外部触发。

公开(公告)号：US20070013422A1

公开(公告)日：2007-01-18

申请号：US11179400

申请日：2005-07-12

Applicant: Quanhong Zhu ,  Don D. Josephson

Inventor： Quanhong Zhu ,  Don D. Josephson

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/05 ,  H03K2005/00156

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract translation: 在一个实施例中，时钟脉冲宽度控制电路包括多个定时器电路，以从输入时钟信号，对应的多个与门产生相应的多个延迟脉冲信号，每个与门从延迟脉冲产生输出信号 信号和输入时钟信号，以及选择电路以选择输出信号之一。

公开(公告)号：US06683483B1

公开(公告)日：2004-01-27

申请号：US10280472

申请日：2002-10-25

Applicant: Jeffrey Paul Witte ,  Quanhong Zhu ,  Don D. Josephson

Inventor： Jeffrey Paul Witte ,  Quanhong Zhu ,  Don D. Josephson

IPC: H03K3017

CPC classification number: H03K5/1565 ,  H03K5/135

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Abstract translation: 两个同步触发器将慢时钟的转换同步到快速时钟。 同步慢时钟版本的状态由时钟在快速时钟边缘的最后一个状态触发器存储。 最后状态触发器通过逻辑与同步慢时钟的版本进行比较，以产生宽度由快速时钟的相位或快速时钟周期确定的宽度的脉冲。

公开(公告)号：US06489834B2

公开(公告)日：2002-12-03

申请号：US09811243

申请日：2001-03-16

Applicant: Samuel D. Naffziger ,  Don D Josephson

Inventor： Samuel D. Naffziger ,  Don D Josephson

IPC: H03K301

CPC classification number: G06F1/32 ,  G01R31/2843 ,  H02J1/14

Abstract: A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption. On-chip control circuitry may be implemented to trigger certain operations to reduce the chip's long-term and/or short-term power consumption upon determination that such power consumption is too high.

Abstract translation: 公开了利用集成电路（“芯片”）功耗的模拟检测来实现功耗管理的系统和方法。 片上电路可以用于检测芯片的模拟电气特性，例如其电压，确定芯片的功耗。 一个实施例利用片上电路来管理芯片的长期，持续的功耗，其包括大约一微秒的功率消耗以及更长的时间帧。 另一实施例利用片上电路来管理芯片的短期功耗，其包括小于一微秒（例如，纳秒时间帧）的功耗。 优选实施例同时实现用于管理长期功耗的电路和用于管理短期功耗的电路。 可以实现片上控制电路以在确定这种功率消耗太高时触发某些操作来减少芯片的长期和/或短期功耗。

公开(公告)号：US06378092B1

公开(公告)日：2002-04-23

申请号：US09418748

申请日：1999-10-15

Applicant: Don D Josephson

Inventor： Don D Josephson

IPC: G01R3128

CPC classification number: G01R31/318541

Abstract: Integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuitry. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.

Abstract translation: 集成电路包括目标电路和测试电路。 目标电路使用时钟信号来传输集成电路内的目标信号。 测试电路在时钟信号的时钟周期内从多个可能的时间在选定的时间对目标信号进行采样。 测试电路响应于指示所选时间的测试信号对目标信号进行采样。