公开(公告)号：US06509788B2

公开(公告)日：2003-01-21

申请号：US09811255

申请日：2001-03-16

Applicant: Samuel D. Naffziger ,  Don D Josephson

Inventor： Samuel D. Naffziger ,  Don D Josephson

IPC: H01J1982

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

公开(公告)号：US06804793B2

公开(公告)日：2004-10-12

申请号：US09811256

申请日：2001-03-16

Applicant: Don D Josephson ,  Samuel D. Naffziger

Inventor： Don D Josephson ,  Samuel D. Naffziger

IPC: G06F104

CPC classification number: G06F1/04

Abstract: A system and method are disclosed which provide an integrated circuit having a clock signal that is dynamically manipulated in response to detected events within the integrated circuit. In one embodiment, the chip includes event detection circuitry that monitors the operation of the chip and detects events that lead to a power disturbance therein. Circuitry may be included for detecting anticipated operation known to trigger an event, as well as for detecting unanticipated events. Additionally, clock manipulator circuitry is included to manipulate the chip's clock signal responsive detection of an event to enable the chip to cope with such event. In response to an event being detected, the clock manipulator circuitry may dynamically manipulate the clock signal in various manners, such as by altering the clock signal's duty cycle, delaying the occurrence of a transition of the clock signal, or altering the clock signal's frequency, as examples.

Abstract translation: 公开了一种系统和方法，其提供具有响应于集成电路内的检测到的事件动态地操纵的时钟信号的集成电路。 在一个实施例中，芯片包括事件检测电路，其监视芯片的操作并检测导致其中的功率干扰的事件。 可以包括用于检测已知触发事件的预期操作以及用于检测意外事件的电路。 此外，包括时钟操纵器电路以操纵芯片的时钟信号以响应事件的检测，以使芯片能够应对这种事件。 响应于检测到的事件，时钟操纵器电路可以以各种方式动态地操纵时钟信号，例如通过改变时钟信号的占空比，延迟时钟信号的转变的发生或改变时钟信号的频率， 作为例子。

公开(公告)号：US06489834B2

公开(公告)日：2002-12-03

申请号：US09811243

申请日：2001-03-16

Applicant: Samuel D. Naffziger ,  Don D Josephson

Inventor： Samuel D. Naffziger ,  Don D Josephson

IPC: H03K301

CPC classification number: G06F1/32 ,  G01R31/2843 ,  H02J1/14

Abstract: A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption. On-chip control circuitry may be implemented to trigger certain operations to reduce the chip's long-term and/or short-term power consumption upon determination that such power consumption is too high.

Abstract translation: 公开了利用集成电路（“芯片”）功耗的模拟检测来实现功耗管理的系统和方法。 片上电路可以用于检测芯片的模拟电气特性，例如其电压，确定芯片的功耗。 一个实施例利用片上电路来管理芯片的长期，持续的功耗，其包括大约一微秒的功率消耗以及更长的时间帧。 另一实施例利用片上电路来管理芯片的短期功耗，其包括小于一微秒（例如，纳秒时间帧）的功耗。 优选实施例同时实现用于管理长期功耗的电路和用于管理短期功耗的电路。 可以实现片上控制电路以在确定这种功率消耗太高时触发某些操作来减少芯片的长期和/或短期功耗。

公开(公告)号：US08975936B2

公开(公告)日：2015-03-10

申请号：US13601119

申请日：2012-08-31

Applicant: Visvesh S. Sathe ,  Samuel D. Naffziger

Inventor： Visvesh S. Sathe ,  Samuel D. Naffziger

IPC: G06F1/04 ,  H03K3/00

CPC classification number: G06F1/10

Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.

Abstract translation: 集成电路包括谐振时钟网络的多个谐振时钟域。 每个谐振时钟域具有至少一个时钟驱动器，其将一部分时钟信号提供给相关联的谐振时钟域。 谐振时钟网络以谐振模式工作，其中电感器连接到谐振时钟域之间边界处的谐振时钟域对。 每个电感器在电感器所连接的一对谐振时钟域中形成具有时钟负载电容的LC电路。

公开(公告)号：US08854100B2

公开(公告)日：2014-10-07

申请号：US13601188

申请日：2012-08-31

Applicant: Visvesh S. Sathe ,  Samuel D. Naffziger ,  Srikanth Arekapudi

Inventor： Visvesh S. Sathe ,  Samuel D. Naffziger ,  Srikanth Arekapudi

IPC: G06F1/04 ,  H03K3/00 ,  H03K19/003

CPC classification number: H03K19/003 ,  G06F1/10

Abstract: A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.

Abstract translation: 用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。 第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。 第一控制信号的有效边沿响应延迟的时钟信号的下降沿。 第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。 第二控制信号的有效边沿响应延迟的时钟信号的上升沿。

公开(公告)号：US08495395B2

公开(公告)日：2013-07-23

申请号：US12881307

申请日：2010-09-14

Applicant: Samuel D. Naffziger

Inventor： Samuel D. Naffziger

IPC: G06F1/00

CPC classification number: G06F1/206 ,  G06F1/3203 ,  Y02D10/16

Abstract: A system includes a plurality of processor cores and a power management unit. The power management unit may be configured to independently control the performance of the processor cores by selecting a respective thermal power limit for each of the plurality of processor cores dependent upon an operating state of each of the processor cores and a relative physical proximity of each processor core to each other processor core. In response to the power management unit detecting that a given processor core is operating above the respective thermal power limit, the power management unit may reduce the performance of the given processor core, and thereby reduce the power consumed by that core.

Abstract translation: 系统包括多个处理器核心和电源管理单元。 功率管理单元可以被配置为通过根据每个处理器核心的操作状态和每个处理器的相对物理接近度来选择对于多个处理器核心中的每一个的相应的热功率限制来独立地控制处理器核心的性能 核心到对方处理器核心。 响应于电源管理单元检测到给定的处理器内核正在高于相应的热功率限制，功率管理单元可以降低给定的处理器核心的性能，从而减少该核心的功耗。

公开(公告)号：US20120159198A1

公开(公告)日：2012-06-21

申请号：US12970172

申请日：2010-12-16

Applicant: Samuel D. Naffziger ,  John P. Petry ,  Kiran Bondalapati

Inventor： Samuel D. Naffziger ,  John P. Petry ,  Kiran Bondalapati

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target.

Abstract translation: 提供了一种处理器功率限制器和方法。 处理器包括被配置为存储处理器功率目标的第一可编程位置。 功率监视器被配置为估计处理器内的测量功率耗散。 功率控制器被配置为基于功率目标和测量的功率耗散来调整处理器功率参数。 处理器可以包括用于操作系统的接口。 可以将第二可编程位置配置为存储由操作系统可访问的软件处理器功率目标。 处理器还可以包括用于外部代理的边带接口。 可以将第三可编程位置配置为存储由外部代理可访问的代理处理器功率目标。 功率控制器可以被配置为调整处理器核心电压和/或频率，使得所测量的功率保持在处理器功率目标，软件处理器功率目标和代理处理器功率目标之下。

公开(公告)号：US08195962B2

公开(公告)日：2012-06-05

申请号：US12268531

申请日：2008-11-11

Applicant: Samuel D. Naffziger ,  Sebastien J. Nussbaum

Inventor： Samuel D. Naffziger ,  Sebastien J. Nussbaum

IPC: G06F1/32 ,  G06F1/26 ,  G06F11/30

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F9/50 ,  Y02D10/16 ,  Y02D10/22

Abstract: A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.

Abstract translation: 一种在最大化处理器性能的同时控制功耗的方法。 该方法包括：在第一操作状态下的操作的时间间隔中，确定处理器的一个或多个核心期间消耗的功率量，基于在该时间间隔中消耗的功率量来计算功率误差，获得 通过将功率误差添加到来自前一时间间隔的功率误差项，以及将功率误差项与至少第一误差阈值进行比较来计算间隔的功率误差项。 如果功率误差项在至少部分由第一误差阈值限定的范围之外，则该方法退出第一操作状态并进入第二操作状态。 如果功率误差项在至少部分地由第一误差阈值限定的范围内，则操作在第一操作状态下继续。

公开(公告)号：US08193799B2

公开(公告)日：2012-06-05

申请号：US12236003

申请日：2008-09-23

Applicant: Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

Inventor： Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

IPC: B23K11/24

CPC classification number: H01L25/16 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0262 ,  H05K2201/10378 ,  Y10T307/406 ,  H01L2224/0401

Abstract: A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

Abstract translation: 公开了一种包括被称为集成电路插入器的电子设备的装置。 集成电路包括电压调节器模块。 插入器附接到诸如另一集成电路的电子设备，并且便于对电子设备的电力的控制和分配。 集成电路插入器还可以在附接的电子设备和另一电子设备之间进行信令。 集成电路插入器上的电压调节器模块可以被配置为向附接的电子设备提供电压参考信号。 根据电子设备的工作要求，可以使能或禁止由集成电路插入器产生电压参考信号，并且可以调节电压参考信号的值。

公开(公告)号：US20120110352A1

公开(公告)日：2012-05-03

申请号：US12915361

申请日：2010-10-29

Applicant: Alexander Branover ,  Samuel D. Naffziger

Inventor： Alexander Branover ,  Samuel D. Naffziger

IPC: G06F1/26 ,  H01L37/00

CPC classification number: G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.

Abstract translation: 公开了一种用于处理节点的每节点热控制的装置和方法。 该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制， 其中所述第一检测温度与所述多个处理节点中的一个相关联。 功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。