公开(公告)号：US06400216B1

公开(公告)日：2002-06-04

申请号：US09718402

申请日：2000-11-24

Applicant: Hack Soo Kim ,  Saeng Hwan Kim

Inventor： Hack Soo Kim ,  Saeng Hwan Kim

IPC: H01J1982

CPC classification number: G11C11/5628 ,  G11C7/06

Abstract: A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a reliability of the apparatus, and reduces the power-consumption. The multi-driving apparatus includes: a level detection circuit block which receives a step-up voltage VPP or a back-bias voltage VBB as an input, and detects different level potentials; a control circuit block for controlling an operation of each generator according to a detected potential by the level detection circuit block; an oscillation circuit block which is oscillated by an enable signal being output from the control circuit block, and generates electric vibrations; and a generation circuit block which receives a control signal from the control circuit block as an input, and is comprised of a plurality of generators being driven by an oscillation output from the oscillation circuit block.

Abstract translation: 通过多电平检测的多驱动装置，其为了有效地操作电压产生电路中的电压发生器而使电压检测电平多次化，使电平波动最小化，降低对装置的总体操作影响的噪声，提高了可靠性 该设备，并降低功耗。 多驱动装置包括：电平检测电路块，其接收升压电压VPP或反偏压VBB作为输入，并检测不同的电平电位; 控制电路块，用于根据电平检测电路块的检测电位来控制每个发生器的操作; 振荡电路块，其通过从控制电路块输出的使能信号振荡，并产生电振动; 以及生成电路块，其从控制电路块接收控制信号作为输入，并且包括由振荡电路块的振荡输出驱动的多个发生器。

公开(公告)号：US06369641B1

公开(公告)日：2002-04-09

申请号：US09668439

申请日：2000-09-22

Applicant: Brian J. McNamara ,  Heinz Banzer ,  Ludger Verweyen

Inventor： Brian J. McNamara ,  Heinz Banzer ,  Ludger Verweyen

IPC: H01J1982

CPC classification number: H03K17/145 ,  G05F3/205 ,  H03K17/302 ,  H03K17/687 ,  H03K17/693

Abstract: In one aspect, a bias circuit includes a rectifier, a negative bias level setter, and a negative bias extractor. The rectifier has a rectifier input and a rectifier output. The rectifier is configured to produce at the rectifier output a negative rectified voltage signal from an alternating input signal applied at the rectifier input. The negative bias level setter couples to the rectifier output and provides a path for current establishing the negative rectified voltage signal produced at the rectifier output. The negative bias extractor has an extractor output and an extractor input coupled to the rectifier output. The negative bias extractor is configured to produce at the extractor output a substantially constant negative bias signal from the negative rectified voltage signal produced at the rectifier output. In another aspect, a bias circuit includes a biasing output coupled between a positive voltage source and a negative voltage source, and a switching circuit coupled between the positive voltage source and the biasing output. The switching circuit is configured to define two or more different current paths through the switching circuit and thereby produce two or more respective biasing states at the biasing output.

Abstract translation: 一方面，偏置电路包括整流器，负偏置电平设定器和负偏压提取器。 整流器具有整流器输入和整流器输出。 整流器被配置为在整流器输出端产生来自在整流器输入端施加的交流输入信号的负整流电压信号。 负偏置电平设置器耦合到整流器输出，并提供用于建立在整流器输出处产生的负整流电压信号的电流的路径。 负偏压提取器具有抽出器输出和耦合到整流器输出的提取器输入。 负偏压提取器被配置为在提取器处产生来自在整流器输出端产生的负整流电压信号的基本恒定的负偏置信号。 在另一方面，偏置电路包括耦合在正电压源和负电压源之间的偏置输出以及耦合在正电压源和偏置输出之间的开关电路。 开关电路被配置为限定通过开关电路的两个或更多个不同的电流路径，从而在偏置输出处产生两个或更多个相应的偏置状态。

公开(公告)号：US06290953B1

公开(公告)日：2001-09-18

申请号：US08584760

申请日：1996-01-11

Applicant: David J. Ballance ,  Michael G. Courtney ,  Christopher J. A. Finnis ,  Darrell Sleep

Inventor： David J. Ballance ,  Michael G. Courtney ,  Christopher J. A. Finnis ,  Darrell Sleep

IPC: H01J1982

CPC classification number: C12N9/1077 ,  A61K38/00 ,  A61K47/6815

Abstract: A method of modulating cellular proliferation by the application of a thymidine phosphorylase to an organism. In a further aspect of the subject method, the thymidine phosphorylase is a conjugate which includes a targeting portion adapted to target the conjugate to a specific cell type or anatomical location. The thymidine phosphorylase has a thymidine phosphorylase activity of at least about 5%, preferably at least about 50% and, most preferably, at least about 90%, of the native E. coli enzyme.

Abstract translation: 通过将胸苷磷酸化酶应用于生物来调节细胞增殖的方法。 在本发明方法的另一方面，胸苷磷酸化酶是包含适于将缀合物靶向特定细胞类型或解剖位置的靶向部分的缀合物。 胸苷磷酸化酶具有至少约5％，优选至少约50％，最优选至少约90％的天然大肠杆菌酶的胸苷磷酸化酶活性。

公开(公告)号：US06271712B1

公开(公告)日：2001-08-07

申请号：US09287279

申请日：1999-04-07

Applicant: Alan Richard Ball

Inventor： Alan Richard Ball

IPC: H01J1982

CPC classification number: H02M7/217 ,  H02M3/1588 ,  H02M3/33592 ,  Y02B70/1466 ,  Y02B70/1475

Abstract: A synchronous rectifier circuit (10) includes a polarity comparator (14) that generates a signal to a driver circuit (16) for controlling the voltage at the gate of a power MOSFET (60). The power MOSFET (60) is switched to operate in the conduction mode and short out a parasitic diode (62) when the diode is forward biased. The power MOSFET (60) is switched to operate in the nonconduction mode when the parasitic diode (62) is reverse biased. A bias supply circuit (12) uses a capacitor (70) to generate a regulated internal bias that provides power to the polarity comparator (14) and to the driver circuit (16). The internal bias allows the power MOSFET (60) to provide a current conduction that is substantially isolated from the changes in voltage levels at the terminals (64, 66) of the synchronous rectifier circuit (10).

Abstract translation: 同步整流电路（10）包括极性比较器（14），其向驱动电路（16）产生信号，用于控制功率MOSFET（60）的栅极处的电压。 当二极管被正向偏置时，功率MOSFET（60）被切换为工作在导通模式并使寄生二极管（62）短路。 当寄生二极管（62）被反向偏置时，功率MOSFET（60）被切换为工作在非导通模式。 偏置电源电路（12）使用电容器（70）产生向极性比较器（14）和驱动器电路（16）提供电力的调节内部偏置。 内部偏置允许功率MOSFET（60）提供与同步整流电路（10）的端子（64,66）处的电压电平的变化基本隔离的电流传导。

公开(公告)号：US06690226B2

公开(公告)日：2004-02-10

申请号：US09863789

申请日：2001-05-22

Applicant: Yasuhiro Takai

Inventor： Yasuhiro Takai

IPC: H01J1982

CPC classification number: G05F3/205 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a substrate potential generating circuit (800) is provided. The substrate potential generating circuit (800) can include a pump circuit (820), an oscillator circuit (801) and a substrate potential detector circuit (300). Substrate potential detector circuit (300) can include a voltage divider (301), differential amplifier (310), and a buffer circuit (320). Voltage divider (301) can provide a detect potential determined by the difference between an internally generated reference potential and a substrate potential. Differential amplifier (310) can receive the detect potential and a reference potential as differential inputs and may produce a substrate potential detect signal. The internally generated reference potential may be generated by a reference generator (900), that may include a reference device (918) and a compensation device (920). The internally generated reference potential may have reduced process and temperature dependency. Thus, a substrate potential can be accurately regulated.

Abstract translation: 提供了具有基板电位产生电路（800）的半导体器件。 衬底电位产生电路（800）可以包括泵电路（820），振荡器电路（801）和衬底电位检测器电路（300）。 衬底电位检测器电路（300）可以包括分压器（301），差分放大器（310）和缓冲电路（320）。 分压器（301）可以提供由内部产生的参考电位和衬底电位之间的差确定的检测电位。 差分放大器（310）可以接收检测电位和参考电位作为差分输入，并可产生衬底电位检测信号。 内部产生的参考电位可以由参考发生器（900）产生，其可以包括参考装置（918）和补偿装置（920）。 内部产生的参考电位可能具有降低的过程和温度依赖性。 因此，可以精确地调节衬底电位。

公开(公告)号：US06411155B2

公开(公告)日：2002-06-25

申请号：US09756389

申请日：2001-01-08

Applicant: Robert Pezzani

Inventor： Robert Pezzani

IPC: H01J1982

CPC classification number: H01L27/08 ,  H01L21/761 ,  H01L27/0814

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract translation: 单片组件包括在第一导电类型的低掺杂半导体晶片的整个厚度上形成的垂直功率半导体元件，其底表面均匀地涂覆有金属化。 这些部件中的至少一些，所谓的自主部件，形成在基板的绝缘部分中，其侧面绝缘由第二导电类型的扩散壁提供，并且其底部通过插入在底表面 的基底和金属化。

公开(公告)号：US06744300B2

公开(公告)日：2004-06-01

申请号：US10277707

申请日：2002-10-23

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H01J1982

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06525593B1

公开(公告)日：2003-02-25

申请号：US09935454

申请日：2001-08-22

Applicant: Monte Mar

Inventor： Monte Mar

IPC: H01J1982

CPC classification number: G06F1/32 ,  G06F1/08 ,  G06G7/06 ,  H03B5/364 ,  H03F1/0261 ,  H03F3/45183 ,  H03F2203/45454 ,  H03F2203/45471 ,  H03F2203/45476 ,  H03F2203/45504 ,  H03K3/012 ,  H03K3/014 ,  H03K3/02315

Abstract: A method and apparatus for local and global power management in a programmable analog circuit. Specifically, the present invention describes an array of programmable analog blocks. Each block contains current mirror circuits that are coupled in parallel fashion. The mirror circuits function to increase current consumption in a corresponding operational amplifier more current when enabled. Global power management is achieved by increasing and decreasing the bias voltage that is applied to the array. Global configuration bits select the bias voltage value, including electrically disabling the bias voltage from the array of programmable analog blocks. Local power management is provided by enabling or disabling mirror circuits with local configuration bits to adjust the performance in an operational amplifier contained within a corresponding programmable analog block. A microcontroller controls the local and global management of power through the programmable analog block.

Abstract translation: 一种用于可编程模拟电路中的局部和全局电源管理的方法和装置。 具体地，本发明描述了可编程模拟块的阵列。 每个块包含以并行方式耦合的电流镜像电路。 镜像电路用于在使能时增加相应运算放大器中的电流消耗。 通过增加和减少应用于阵列的偏置电压来实现全局功率管理。 全局配置位选择偏置电压值，包括从可编程模拟块阵列中电压禁止偏置电压。 通过启用或禁用具有本地配置位的镜像电路来调整包含在相应的可编程模拟块中的运算放大器的性能来提供本地电源管理。 微控制器通过可编程模拟模块控制电源的本地和全局管理。

公开(公告)号：US06429732B1

公开(公告)日：2002-08-06

申请号：US09698965

申请日：2000-10-27

Applicant: Kerry D. Tedrow ,  Jeffrey J. Evertt

Inventor： Kerry D. Tedrow ,  Jeffrey J. Evertt

IPC: H01J1982

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A low frequency oscillator is described. The low frequency oscillator has a bias circuit including a metal-oxide semiconductor (MOS) resistor. A biased ring oscillator is coupled to the bias circuit. The biased ring oscillator includes multiple current limiting transistors.

公开(公告)号：US06509788B2

公开(公告)日：2003-01-21

申请号：US09811255

申请日：2001-03-16

Applicant: Samuel D. Naffziger ,  Don D Josephson

Inventor： Samuel D. Naffziger ,  Don D Josephson

IPC: H01J1982

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.