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    Assigning work from multiple sources to multiple sinks given assignment constraints
    1.
    发明授权
    Assigning work from multiple sources to multiple sinks given assignment constraints 失效
    给定分配约束将工作从多个源分配给多个汇点

    公开(公告)号：US08532129B2

    公开(公告)日：2013-09-10

    申请号：US12650120

    申请日：2009-12-30

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/28

    CPC分类号： H04L49/9047

    摘要： Assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device is provided. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

    摘要翻译： 提供了诸如数据分组的工作，诸如诸如网络处理设备中的数据队列的多个源到网络处理设备中的诸如处理器线程的多个接收器。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports
    2.
    发明授权
    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 有权
    STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能

    公开(公告)号：US08130792B2

    公开(公告)日：2012-03-06

    申请号：US11467848

    申请日：2006-08-28

    申请人： Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

    发明人： Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

    IPC分类号： H04J3/00 ,  H04J3/02

    CPC分类号： H04J3/1611 ,  H04J3/0685 ,  H04J3/22 ,  H04J2203/0089

    摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    摘要翻译： 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

    Controller for multiple instruction thread processors
    3.
    发明授权
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US08006244B2

    公开(公告)日：2011-08-23

    申请号：US10915983

    申请日：2004-08-11

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

    Indicating last data buffer by last bit flag bit
    4.
    发明授权
    Indicating last data buffer by last bit flag bit 有权
    用最后一位标志位指示最后一个数据缓冲区

    公开(公告)号：US07627701B2

    公开(公告)日：2009-12-01

    申请号：US12120419

    申请日：2008-05-14

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F5/00 ,  G06F15/16

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Systems and methods for rate-limited weighted best effort scheduling
    7.
    发明授权
    Systems and methods for rate-limited weighted best effort scheduling 失效
    速率限制加权最佳努力调度的系统和方法

    公开(公告)号：US07474662B2

    公开(公告)日：2009-01-06

    申请号：US11119329

    申请日：2005-04-29

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L47/623 ,  H04L47/50 ,  H04L47/568

    摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.

    摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。 多个不同流中的每一个都具有相关联的调度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

    SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS
    9.
    发明申请
    SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
    多框控制块的系统和方法

    公开(公告)号：US20080147995A1

    公开(公告)日：2008-06-19

    申请号：US12039304

    申请日：2008-02-28

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    IPC分类号： G06F12/00

    CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

    摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。